IT201700053915A1 - Procedimento di packaging di prodotti a semiconduttore, prodotto ed utensile di stampaggio corrispondenti - Google Patents

Procedimento di packaging di prodotti a semiconduttore, prodotto ed utensile di stampaggio corrispondenti

Info

Publication number
IT201700053915A1
IT201700053915A1 IT102017000053915A IT201700053915A IT201700053915A1 IT 201700053915 A1 IT201700053915 A1 IT 201700053915A1 IT 102017000053915 A IT102017000053915 A IT 102017000053915A IT 201700053915 A IT201700053915 A IT 201700053915A IT 201700053915 A1 IT201700053915 A1 IT 201700053915A1
Authority
IT
Italy
Prior art keywords
product
molding tool
semiconductor products
corresponding molding
packaging procedure
Prior art date
Application number
IT102017000053915A
Other languages
English (en)
Inventor
Roberto Rossi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT102017000053915A priority Critical patent/IT201700053915A1/it
Publication of IT201700053915A1 publication Critical patent/IT201700053915A1/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
IT102017000053915A 2017-05-18 2017-05-18 Procedimento di packaging di prodotti a semiconduttore, prodotto ed utensile di stampaggio corrispondenti IT201700053915A1 (it)

Priority Applications (1)

Application Number Priority Date Filing Date Title
IT102017000053915A IT201700053915A1 (it) 2017-05-18 2017-05-18 Procedimento di packaging di prodotti a semiconduttore, prodotto ed utensile di stampaggio corrispondenti

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000053915A IT201700053915A1 (it) 2017-05-18 2017-05-18 Procedimento di packaging di prodotti a semiconduttore, prodotto ed utensile di stampaggio corrispondenti

Publications (1)

Publication Number Publication Date
IT201700053915A1 true IT201700053915A1 (it) 2018-11-18

Family

ID=59859556

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000053915A IT201700053915A1 (it) 2017-05-18 2017-05-18 Procedimento di packaging di prodotti a semiconduttore, prodotto ed utensile di stampaggio corrispondenti

Country Status (1)

Country Link
IT (1) IT201700053915A1 (it)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091341A (en) * 1989-05-22 1992-02-25 Kabushiki Kaisha Toshiba Method of sealing semiconductor device with resin by pressing a lead frame to a heat sink using an upper mold pressure member
JPH05291459A (ja) * 1992-04-07 1993-11-05 Fujitsu Ltd 半導体装置及びその製造方法
JPH10329461A (ja) * 1997-05-29 1998-12-15 Nec Yamagata Ltd 半導体装置及びその製造方法
JPH11150216A (ja) * 1997-11-19 1999-06-02 Denso Corp 樹脂封止型半導体部品及びその製造方法
US20030143780A1 (en) * 2001-12-07 2003-07-31 Kenichi Shirasaka Method and apparatus for manufacture and inspection of semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091341A (en) * 1989-05-22 1992-02-25 Kabushiki Kaisha Toshiba Method of sealing semiconductor device with resin by pressing a lead frame to a heat sink using an upper mold pressure member
JPH05291459A (ja) * 1992-04-07 1993-11-05 Fujitsu Ltd 半導体装置及びその製造方法
JPH10329461A (ja) * 1997-05-29 1998-12-15 Nec Yamagata Ltd 半導体装置及びその製造方法
JPH11150216A (ja) * 1997-11-19 1999-06-02 Denso Corp 樹脂封止型半導体部品及びその製造方法
US20030143780A1 (en) * 2001-12-07 2003-07-31 Kenichi Shirasaka Method and apparatus for manufacture and inspection of semiconductor device

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