IT1306182B1 - PROCEDURE FOR THE SELECTIVE ANODIZATION IN TWO PHASES OF A SEMICONDUCTIVE STRATOD FOR THE FORMATION OF POROUS SILICON. - Google Patents

PROCEDURE FOR THE SELECTIVE ANODIZATION IN TWO PHASES OF A SEMICONDUCTIVE STRATOD FOR THE FORMATION OF POROUS SILICON.

Info

Publication number
IT1306182B1
IT1306182B1 IT1999RM000497A ITRM990497A IT1306182B1 IT 1306182 B1 IT1306182 B1 IT 1306182B1 IT 1999RM000497 A IT1999RM000497 A IT 1999RM000497A IT RM990497 A ITRM990497 A IT RM990497A IT 1306182 B1 IT1306182 B1 IT 1306182B1
Authority
IT
Italy
Prior art keywords
stratod
semiconductive
phases
procedure
formation
Prior art date
Application number
IT1999RM000497A
Other languages
Italian (it)
Inventor
Marco Balucani
Vitaly Bondarenko
Leonid Dolgyi
Aldo Ferrari
Giulio Lamedica
Valentina Yakovtseva
Original Assignee
Shine Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shine Spa filed Critical Shine Spa
Priority to IT1999RM000497A priority Critical patent/IT1306182B1/en
Publication of ITRM990497A0 publication Critical patent/ITRM990497A0/en
Priority to PCT/IT2000/000330 priority patent/WO2001009933A1/en
Priority to AU67238/00A priority patent/AU6723800A/en
Publication of ITRM990497A1 publication Critical patent/ITRM990497A1/en
Application granted granted Critical
Publication of IT1306182B1 publication Critical patent/IT1306182B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Silicon Compounds (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
IT1999RM000497A 1999-08-02 1999-08-02 PROCEDURE FOR THE SELECTIVE ANODIZATION IN TWO PHASES OF A SEMICONDUCTIVE STRATOD FOR THE FORMATION OF POROUS SILICON. IT1306182B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT1999RM000497A IT1306182B1 (en) 1999-08-02 1999-08-02 PROCEDURE FOR THE SELECTIVE ANODIZATION IN TWO PHASES OF A SEMICONDUCTIVE STRATOD FOR THE FORMATION OF POROUS SILICON.
PCT/IT2000/000330 WO2001009933A1 (en) 1999-08-02 2000-08-02 Process for the two-step selective anodizing of a semiconductor layer for forming porous silicon
AU67238/00A AU6723800A (en) 1999-08-02 2000-08-02 Process for the two-step selective anodizing of a semiconductor layer for forming porous silicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1999RM000497A IT1306182B1 (en) 1999-08-02 1999-08-02 PROCEDURE FOR THE SELECTIVE ANODIZATION IN TWO PHASES OF A SEMICONDUCTIVE STRATOD FOR THE FORMATION OF POROUS SILICON.

Publications (3)

Publication Number Publication Date
ITRM990497A0 ITRM990497A0 (en) 1999-08-02
ITRM990497A1 ITRM990497A1 (en) 2001-02-02
IT1306182B1 true IT1306182B1 (en) 2001-05-30

Family

ID=11406921

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1999RM000497A IT1306182B1 (en) 1999-08-02 1999-08-02 PROCEDURE FOR THE SELECTIVE ANODIZATION IN TWO PHASES OF A SEMICONDUCTIVE STRATOD FOR THE FORMATION OF POROUS SILICON.

Country Status (3)

Country Link
AU (1) AU6723800A (en)
IT (1) IT1306182B1 (en)
WO (1) WO2001009933A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5669864A (en) * 1979-11-09 1981-06-11 Japan Electronic Ind Dev Assoc<Jeida> Thin-film transistor
FR2564241B1 (en) * 1984-05-09 1987-03-27 Bois Daniel METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS
EP0226091A3 (en) * 1985-12-17 1989-09-13 Texas Instruments Incorporated Semiconductor isolation using trenches and oxidation of anodized silicon sublayer
JP2794678B2 (en) * 1991-08-26 1998-09-10 株式会社 半導体エネルギー研究所 Insulated gate semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
ITRM990497A0 (en) 1999-08-02
ITRM990497A1 (en) 2001-02-02
WO2001009933A1 (en) 2001-02-08
AU6723800A (en) 2001-02-19

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