WO2001009933A1

WO2001009933A1 - Process for the two-step selective anodizing of a semiconductor layer for forming porous silicon

Info

Publication number: WO2001009933A1
Application number: PCT/IT2000/000330
Authority: WO
Inventors: Marco Balucani; Vitaly Bondarenko; Leonid Dolgyi; Aldo Ferrari; Giulio Lamedica; Valentina Yakovtseva
Original assignee: Shine S.P.A.
Priority date: 1999-08-02
Filing date: 2000-08-02
Publication date: 2001-02-08
Also published as: ITRM990497A1; ITRM990497A0; IT1306182B1; AU6723800A

Abstract

A process for the two-step selective anodization of a semiconductor layer for forming porous silicon in particular provides the selective anodization of one or more regions of N+(+) semiconducting material inside Ζ/N?+(+)/N(-)¿-type structures for semiconductor integrated circuits, by means of a first step of constant current anodization wherein a working voltage value is determeined, and a second step of anodization with constant voltage value equal to the working voltage value determined in the constant current anodization step.

Description

PROCESS FOR THE TWO STEP SELECTIVE ANODISING OF A SEMICONDUCTOR LAYER FOR FORMING POROUS SILICON

DESCRIPTION

The present invention refers to a process for the two-step selective anodization of a semiconductor layer for forming porous silicon. In particular, this invention refers to a process of selective anodization of one or more regions of N⁺⁽⁺⁾ semiconducting material, for forming porous silicon, inside Φ/ ^ N^-type structures for semiconductor integrated circuits, under the Φ symbol being referenced the silicon which can be N-type, or N^"-type, or P-type, or P^'-type or, at last, Sii-type. Under Sii silicon, intrinsic silicon that is non-doped silicon will be meant.

Since a uniform definition of doping levels does not exist in literature, in the following description:

• under P^'silicon, silicon showing a dopant (e.g. Boron) atom concentration lower than 10¹⁵ atoms/cm³ will be meant;

• under P-silicon, silicon showing a dopant (e.g. Boron) atom concentration between 10¹⁵ and 10¹⁷ atoms/cm³ will be meant;

• under N^"-silicon, silicon showing a dopant (e.g. Phosphorus, Antimony, Arsenic) atom concentration lower than 10¹⁵ atoms/cm³ will be meant; • under N-silicon, silicon showing a dopant (e.g. Phosphorus, Antimony, Arsenic) atom concentration between 10¹⁵ and 10¹⁷ atoms/cm³ will be meant;

• under N⁺-silicon, silicon showing a dopant (e.g. Phosphorus, Antimony, Arsenic) atom concentration between 10¹⁷ and 10¹⁹ atoms/cm³ will be meant; and

• under N^-silicon, at last, silicon showing a dopant (e.g. Phosphorus, Antimony, Arsenic) atom concentration greater than 10¹⁹ atoms/cm³ will be meant.

In the following description and in the drawings, under the N^(_) symbol, silicon which can be N-type or N^"-type will be meant. Likewise, under the N⁺⁽⁺⁾ symbol, silicon which can be N^-type or N^-type will be meant. Under the P^("} symbol, silicon which can be P-type or P^"-type will be meant. The application field of the invention refers to the manufacturing of silicon- on-insulator structures (SOI), that is semiconductor structures showing silicon regions electrically isolated from the substrate by an oxidized porous silicon. This manufacturing process is known under the FIPOS term (Full Isolation by Porous Oxidized Silicon). The present invention in particular refers to processes for manufacturing

FIPOS structures based upon the selective anodization of the N⁺⁽⁺⁾ layer inside a Φ/ ^ N'^"-¹ structure. These processes provide a first step wherein doped silicon is transformed into porous silicon (anodization step) and a second step wherein porous silicon is transformed into silicon dioxide (oxidation step) The formation of these structures is obtained by exploiting the high chemical reactivity of porous silicon The easiness m oxidizing of porous silicon compared to "bulk" silicon allows oxidizing a porous silicon layer buπed between two layers of silicon

The semiconductor devices manufactured by means of SOI technology offer several advantages compared to the conventional technology of silicon ("bulk silicon") Among the mam advantages of SOI technology, the power consumption decrease, the elimination of the "latch-up" effect in CMOS circuits, a faster device operation thanks to the decrease m parasitic capacitances and a higher immunity to ionizing radiations may be found

SOI devices may be classified according to the thickness of silicon layer over the oxide and to the thickness of buπed oxide This kind of classifications are mentioned for example m the book "Physical and technical problems of SOI structures and devices" published by J P Colmge, V S Lysenko and A N Nazarov,

NATO ASI, seπes High Technology, v 4 or in Dataquest market analysis of 24 Apπl 1998 "SOI wafer market trends application perspectives" wπtten by Clark Fuhs and Takashi Ogawa

A current disadvantage of SOI technology is that SOI structures cannot be manufactured wherein thicknesses different between them of the buπed insulating silicon dioxide layer and of the silicon layer over the oxide inside the same chip (thickness modulation) may be manufactured In fact, by means of BESOI (Bonded and Etch back Silicon On Insulator) technology or the vaπations thereof such as SMART CUT technique, it is impossible to modulate thickness since two wafer must perfectly match to weld together and obtain a SOI-type wafer SLMOX technique which enables manufactuπng SOI wafer by implanting oxigen could m pπnciple perform a thickness modulation by means of a masking procedure duπng the implantation step, but, up to now, it apparently has not been performed also because in order to obtain high thicknesses of buπed oxide, doses should be quite high, b damaging the silicon over it For this reason with SIMOX technique structures with buπed oxide lower than one micron tend to be manufactured and thm oxide layers of about hundreds of nm tend to be obtained for reducing damage of the silicon layer over the oxide and reducing time of thermal treatment

This limitation is in conflict with the important need of integrating analogous and/or digital devices and/or low, medium and high power devices on the same integrated circuit, which would provide a high flexibility, an increase m reliability and a cost reduction for the electronic system compared to "bulk silicon" devices The present invention overcomes the above illustrated problems of prior art since it provides a process of selective anodization of one or more regions of ^"^ semiconducting material, for forming porous silicon, inside Φ/N⁺⁽⁺⁾/N^(")-type structures for semiconductor integrated circuits, characterized in that it comprises the steps of: performing a first step of constant current anodization, by determining the value of a working voltage during this constant current anodization; and performing a second step of constant voltage anodization, the value of said constant voltage being equal to the value of working voltage determined in the constant current anodization step.

Furthermore a process for manufacturing FIPOS structures based upon the selective anodization of one or more regions of N^"1"^ semiconducting material is also provided, for forming porous silicon inside Φ/N⁺⁽⁺⁾/N^(")-type structures for semiconductor integrated circuits and based upon the subsequent oxidation of said porous silicon, characterized in that said selective anodization is performed according to the above-mentioned process of selective anodization.

A FIPOS structure obtained by means of the above-provided process is furthermore provided.

Advantageous features of the present invention are provided in the dependent claims thereof.

The anodization process according to the present invention inside SOI structures is based upon the preferred anodization of a N⁺⁽⁺⁾ buried layer in a Φ/N⁺⁽⁺⁾/N^(")-type structure. This process is selective-type compared to the N^-¹ buried layer, since the working voltage necessary to transform Sii or P^(_) or N^-¹ silicon into porous silicon is higher than the working voltage necessary to perform the same process on N^-type silicon.

The starting substrate can be a N^-type single-crystal wafer or a ^ heavily doped single-crystal wafer with N^H lightly doped epitaxial layer. In particular, the process allows transforming one or more N^"1"^ buried layer with thicknesses even different between them in order to obtain one or more layers of silicon oxide insulator with different thickness (thickness modulation), respectively. In this way the integration of different devices inside the same chip is made much easier.

A further advantage of the anodization process according to the present invention is that it will be possible making the transformation process of silicon into porous silicon to interrupt automatically when the whole region of N⁺⁽"⁾ silicon is transformed into porous silicon.

Another advantage is that it is possible manufacturing a uniform layer of porous silicon with a prefixed porosity of the

sandwich structure.

The anodization process, according to the following invention, is performed in two steps. A first step (constant current step) provides the utilization of a constant current, so as to allow obtaining porous silicon with a determined porosity (equal to 50%) - 60%) ) starting from N ^" or N^-type silicon and so as to allow determining a working voltage for the subsequent step.

A second step (constant voltage step) provides the utilization of a constant voltage, equal to the working voltage value determined in the preceding step. During this second step current decreases. By means of the present invention both the position of the buried insulating silicon dioxide layer and the thickness of this buried layer may be freely determined. Application modes of the present invention for example provide manufacturing of CMOS integrated circuits wholly by SOI technology, or CMOS- type circuits the pMOS portion thereof is manufactured by SOI technology and the nMOS portion thereof is in bulk silicon and/or viceversa. BiCMOS (Bipolar/CMOS) structures showing CMOS portion manufactured by SOI technology and Bipolar portion in bulk silicon could also be provided.

An additional advantage provided by the possibility of modulating the buried oxide thickness is given by the possibility of integrating devices for different application modes in the same integrated circuit. By way of example circuits can be mentioned wherein a thin oxide layer for the devices of the digital portion of the integrated circuit and a thick layer of buried oxide for the devices of the analogic portion of the integrated circuit are provided.

Other advantages, features and application modes will be evident from the following detailed description of the invention, provided by embodiments by way of example and not for limitative purposes. The figures of the enclosed drawings will be referred to, which in a schematic way illustrate the situation of the performed technological steps, to allow a greater comprehension of the inventive core of the present invention, wherein: Figs. 1 to 9 show subsequent steps of the process according to the invention so as to obtain one or more regions of silicon dioxide (SiO₂) underneath single- crystal silicon islands, in particular:

Fig. 1 shows a partial cross-sectional view of a single-crystal silicon wafer showing a photoresist layer and so as to provide a first implantation of a heavily doped region over the wafer lower surface;

Fig. 2 shows the wafer during the subsequent implantation of a heavily doped region over the wafer upper surface; Fig. 3 shows the structure of Fig. 2 after an annealing operation; Fig. 4 shows a subsequent implantation step of a heavily doped region; Fig. 5 shows a subsequent annealing step;

Fig. 6 shows a subsequent deposition of an epitaxial silicon layer; Fig. 7 shows the wafer after a partial removal of the epitaxial layer;

Fig. 8 shows the structure obtained later after anodization; and Fig. 9 shows the structure obtained later after oxidation and removal of the protective mask.

Fig. 10 shows the variation of porosity of porous silicon in terms of current density and kind of electrolyte chosen for a fixed dopant concentration;

Fig 11 shows the variation of porosity of porous silicon in terms of current density and dopant concentration for a fixed electrolytic solution;

Figs. 12A and 12B show voltage and current variation in terms of time during anodization process; Fig. 13 shows some of the features of the obtained oxide layer;

Fig. 14 shows a heavily doped silicon wafer with a lightly doped expitaxial layer;

Figs. 15 to 22 are equivalent to fig. 2 to 9 and refer to a structure related to a substrate comprising a N⁺⁽⁺⁾ heavily doped single-crystal silicon wafer whereon a thick layer of N^(_) single-crystal silicon is deposited by epixatial way;

Fig. 23 shows an electrolytic cell utilized in the silicon anodization step; Fig. 24A shows the doping profile variation in terms of a particular implantation;

Fig. 24B shows the doping profile as illustrated in fig. 24A after an epitaxial growth at high temperature; and

Fig. 24C shows the doping profile variation as illustrated in fig. 24A after an epitaxial growth at low temperature.

By firstly referring to Fig. 1, a partial cross-sectional view of single-crystal wafer 101 is shown, hereinafter designated with the term semiconducting substrate. The semiconducting substrate 101, N or N^"-type, is chosen preferably with a resistivity between 4 and 400 Ohm-cm. The upper surface of the substrate 101 is covered with a photoresist layer 102, and after that a ion implantation on the lower surface of the substrate 101 is performed. The photoresist layer 102 aims at preventing possible damages on the surface of the substrate 101 during ion implantation. Prefeπed implantation modes provide the use of Antimony (Sb) or Arsenic (As) atoms with dosing between 9 10¹⁴ and 5^' 10^{l D} cm^"" and energy in the range of 40 and 120 KeV. The implanted atom layer is referenced in figure as numeral 149. After implantation, the photoresist layer 102 is removed and the silicon substrate 101 is chemically cleaned.

In figures 2 to 7 herebelow described, the operating steps apt to define the areas in which creating N⁺⁽⁺⁾ regions to be transformed into porous silicon and then into silicon dioxide (Si0₂) will be illustrated. According to circuit requirements, different time by time, the manufacturing of several oxide thicknesses, different between them, could be necessary. In the following figures an example of two regions with different thickness will be illustrated.

By referring to Fig. 2, the substrate 101, showing the implanted layer 149 referred to in the preceding Fig. 1 on the lower surface thereof, is covered with a new photoresist layer 103, deposited on the upper surface thereof.

By means of photolithographic process an area is defined whereon implantation is performed. This area does not result to be protected by the layer 103. The layer of atoms implanted by this second implantation is designated in figure with numeral 150. Also in this case the implanted material is Antimony or Arsenic preferably. After implantation, the photoresist layer 103 will be removed and the silicon substrate 101 will be chemically cleaned.

Following what has been so far described by referring to Figs. 1 and 2, a thermal treatment is performed to activate the atoms implanted in the region 150, to restore the crystalline structure damaged during implantation and to diffuse dopant atoms.

This thermal treatment, known as "annealing" in literature, can be for example a process at high temperature (over 1100 °C) in oxygen ambient for 30-120 minutes. After this treatment, implantation regions will show as in Fig. 3. In particular, a N^ layer 104 underneath the upper surface of the substrate 101 and a N⁺⁽⁺⁾ layer 105 underneath the lower surface of the substrate 101 will be formed.

An exemplary thickness of the layer 104 can be 1.2 μm, obtained by Antimonic implantation with 60 keV energy with 250 μC/cm² dose and with a thermal treatment in dry oxygen ambient of 1200°C for about 40 minutes.

The layer 105 placed on the lower surface of the substrate 101 is advantageous, since it aims at providing a good electric contact during the following anodization step.

The following Figs. 4 and 5 show the operating steps performed to manufacture in the substrate 101 a second N^+(τ) region with the thickness, for example, lower than that of the region 104 of Fig. 3.

By referring to Fig. 4, the substrate 101 is covered with a new photoresist layer 106, deposited on the upper surface thereof.

By means of photolithographic process an additional area is defined whereon implantation is performed. This area does not result to be protected by the layer 106. The layer of atoms implanted by this third implantation is designated in figure with numeral 151. The implanted material is Antimony or Arsenic preferably. After implantation, the photoresist layer 106 will be removed and the silicon substrate 101 will be chemically cleaned.

An additional annealing is then performed to activate the atoms implanted in the region 151, to restore the crystalline structure damaged during implantation and to diffuse dopant atoms. This thermal treatment can be for example a process at high temperature (between 1100°C and 1220°C) in oxygen ambient for 30-60 minutes. Alternatively, the annealing can be of quick type, performed for few seconds at a temperature between 700°C and 1100°C.

After this treatment, a further N⁺⁽⁺⁾ layer 107 will be obtained, shown in Fig. 5, placed underneath the upper surface of the substrate 101 as well.

The kind of thicknesses and doping levels of N ^"^ regions 104 and 107 is determined by ion implantation regions and by performed thermal treatment.

By way of example, Fig. 24A shows a probable variation of doping profile, that is net doping (atoms/cm³, on y-axis) of the N^"1^ layer 104 or 107 in terms of depth inside the substrate 101 (μm, on x-axis).

The variation of Fig. 24A in particular has been obtained by an amorphization pre-implantation with silicon ions for obtaining an amorphous surface layer with a thickness of about 2500 Angstrom and by a double implantation of Antimony or

Arsenic atoms. By using Antimony the first implantation dose has been about 5 10¹² - 1 10 atoms/cm with 30keV energy, whereas the second implantation dose has been about 1 10¹³ - 2 10¹³ atoms/cm² with 160 keV energy. By using Arsenic the first implantation dose is about 5 10 - 1 10 atoms/cm with 20keV energy, whereas the second implantation energy is about 1 10¹³ - 2 10¹³ atoms/cm² with 110 keV energy.

The layers 104 and 107 are the layers to be converted into porous silicon by means of anodization and the thicknesses thereof determine the thicknesses of final oxide layers. In the embodiment shown in Fig. 5, wherein regions with different thickness are namely present, it is preferable that the dopant surface concentrations differ no more by 40% between one region and the other, because in this way it will be possible to transform both regions into porous silicon by a single anodization process. In fact, later it will be emphasized how the porous silicon porosity depends on the dopant surface concentration, once electrolyte and current density utilized during the subsequent anodization process are fixed. Then, m order that both layers 104 and 107 may be converted into porous silicon with the same process and with predetermined porosity in the 50%>-60% range, it is preferable that these layers have a dopant surface concentration differing no more by above mentioned 40%o.

The thickness of the layers 104 and 107 usually varies between 0.20 and 5.00 μm, whereas the surface concentration varies between T10¹⁸ and 4 10¹⁹ cm^"2.

By referring to Fig. 6, a Sii o P^(_) or N^(_) lightly doped epitaxial layer 108 is shown, grown on the upper surface of the substrate 101 and therefore on the upper surface of the regions 104 and 107. This epitaxial layer 108 represents the layer wherein electronic devices will be manufactured and has a thickness usually varying between 0.05 and 5 μm.

This epitaxial layer is grown so as to perform an abrupt (also called hyperfme) transition between the heavily doped regions 104 and 107 and the epitaxial layer 108. This abrupt transition aims at making easier the complete transformation of the layers 104 and 107 into porous silicon, without altering the structure of the layer 108 over them. In fact, greater is the dopant concentration gradient between the Sii or P^(_) or N^ material and the N⁺⁽⁺⁾ material, greater will be the possibility of obtaining a transformation of the N^ layer into porous silicon without undesired consequences on the Sii or V^ o N^-type epitaxial layer 108.

The epitaxial layer 108 may be grown with any method for growing single- crystal silicon.

The main difficulty in performing an abrupt transition is represented by auto- diffusion, which must be limited as much as possible. The present invention, in a preferred embodiment thereof, utilizes an epitaxial growth process of the layer 108 at low temperature (lower than about 900°C, preferably 700-850°C or firstly by means of a deposition at about 600°C and then at higher temperature between about 700 and about 900°C).

Fig. 24B shows the doping profile for an epitaxial layer grown at a 1100°C temperature on a substrate having as initial doping profile the profile shown in Fig. 24A. The Fig. 24C shows the doping profile for an epitaxial layer grown at low temperature (lower than 900°C) on a substrate having as initial doping profile the profile shown in Fig. 24A.

In both figures net doping (atoms/cm³) is on y-axis whereas doping depth (with μm) is on x-axis. In particular, the negative values of doping depth show the grown epitaxial layer.

During the following process of conversion into porous silicon (anodization) of the N⁺⁽⁺⁾ layers inside the ΦIN^H+W^') structure 108/104(107)7101 , all the silicon having a concentration higher or equal to 10¹⁷ atomi/cm³ is converted into porous silicon.

From the comparative analysis between Figs. 24B and 24C it can then be noted how the slope at curve in the parabolic region thereof is greater in Fig. 24C rather than in Fig. 24B. By referring to Fig. 24B, it can be noted in particular that there is a transition equal to approx. 0.2 μm between the layer 104 (or 107) and the layer 108 wherein doping varies between 10¹⁷ and 10¹⁵ atoms/cm³. This transition has been designated with the dβ symbol in Fig. 24B. By referring to Fig. 24C instead, it can be noted that the transition is highly reduced, equal to approx. 0.05 μm. This transition has been designated with the dc symbol in Fig. 24C.

This reduced (hyperfine) transition is advantageous, since it denotes the presence of an abrupt transition, useful for improving the performance of subsequent anodization and oxidation operations.

Growing the epitaxial layer at a temperature of 600 °C can slow down the growing process as the growth rate of the epitaxial layer is low at this temperature.

This fact could be inconvenient in case of manufacturing layers 108 with high thickness, that is equal to 0.5 μm or more. Thicknesses with these sizes are sometimes necessary for manufacturing SOI devices.

A first possibility of overcoming this problem is given by the material choice. In fact, by utilizing dichlorosilane (SiH₂Cl₂) a growing rate of the epitaxial layer of about 0.5 nm/min. is obtained, whereas by using silane ( SiH₄) this growth rate may be even of 10 nm/min.

A second possibility, instead, is given by performing an epitaxial growth at non-constant temperature. In particular, a first step will have to provide growing a thin layer (0.05 - 0.1 μm) at low temperature (about 600 °C) according what has been so far described, whereas a second step will have to provide growing of a layer at a higher temperature (700-900°C). In this second step, although temperature is higher, the auto-diffusion will be greatly reduced thanks to the presence of the thin layer previously grown at the temperature of about 600°C. The growth at low temperature can be performed for example by UHCVD

(Ultra-High Vacuum Chemical Vapour Deposition), that is by means of a high vacuum chemical vapour deposition. A generic example of using this method is described in the article by B. S. Meyeron "Low Temperature Silicon Epitaxy by

Ultrahigh Vacuum Chemical Vapour Deposition" published on Applied Physics Letter, V.48 (12), 1986, p.797-799.

After growing the layer 108, a protective layer, preferably silicon nitride (Si N₄) is deposited over it. The deposition can be performed by LPCVD (Low Pressure Chemical Vapour Deposition), that is low pressure chemical vapour deposition.

By means of lithographic processes, the desired island structure is obtained, by removing part of the layer 108. A process which can be advantageously utilized is the chemical etching, anisotropic plasma etching in particular, as it allows obtaining islands with vertical sidewalls. This is advantageous, since the presence of islands with vertical sidewalls, i.e. substantially parallelepiped-shaped islands, is prefeπed to the presence of islands with oblique sidewalls, i.e. substantially frustopyramid-shaped islands. In the first case, in fact, islands occupy a well-defined space, and therefore distances between islands could be defined by a lithographic process. On the contrary, in case of frustopyramid-shaped islands they will have to be well spaced between them so as to prevent any dangerous mutual contact.

This protective layer aims at protecting the epitaxial layer 108 against possible effects of subsequent anodization and oxidation processes.

After the photoresist removal and a chemical cleaning process of the substrate, the structure as represented in Fig. 7 is obtained, wherein the protective layer over the epitaxial layer 108 has been designated with 109. At this point the wafer is ready for anodizing the layers 104 and 107 which will be converted into porous silicon.

The anodization process is performed in an electrochemical cell. An exemplary embodiment of this electrochemical cell is represented in Fig. 23. In this figure the whole wafer is schematically designated with numeral 402 and is wet by an electrolitic solution 403. This solution is preferably hydrofluoric-acid based (HF), with a volume concentration preferably between 0.1 % and 50%, deionized water and an additive. This additive can be for example an alcohol, such as ethanol (C₂H₅OH), or isopropyl alcohol (iso-C₃H₇0H).

The wafer acts as anode by a contact 400. For the cathode 401 a non-reagent in the process conducting material, such as platinum, tungsten or nickel, is utilized. On the basis of researches carried out by inventors, a dependence of porous silicon porosity on current density for different kind of electrolyte and different doping levels of silicon to be anodized has been disclosed and determined.

In laboratory tests carried out by inventors, silicon has been anodized with different electrolytic solutions with different current density. The porosity of the several samples has been obtained by measuring weight before and after anodization, by measuring the thickness of the obtained porous silicon and knowing the surface of the region transformed into porous silicon, in particular according to the following equations:

(Equation 1) and

P.. - fin

PPS = Psi ^{' ■} (Equation 2)

S - d

wherein:

P%> is the porosity of porous silicon; pp≤ is the density of porous silicon; psi is the density of single-crystal silicon (known); Pj_n is the initial weight of the sample; P_fi_n is the final weight of the sample after anodization (measured); S is the surface of the region transformed into porous silicon (known); and d is the thickness of the porous silicon layer (measured).

Fig. 10 shows the variation of porosity of porous silicon (in %) in terms of current density (mA/cm²) for three different electrolytic solutions and for a fixed value of the dopant concentration in wafer (4^' 10¹⁸ atoms/cm³).

Fig. 11 shows furthermore the variation of porosity of porous silicon (in %) in terms of current density (mA/cm ) for four different silicon doping levels, shown in the legend of the figure itself. All the four doping levels in the figure refer to a fixed electrolytic solution, composed (in volume concentration) by 25%> by HF (by 50%) and by 75% by ethanol (C₂H₅OH).

The anodization process is performed in two steps. A first step is performed with constant current and aims at determining the working voltage to be fixed in the following step which will be performed with constant potential. The choice of the initial value of constant current depends on the silicon porosity percentage which is wanted to be obtained. The value of current density will be probably determined by diagrams such as those shown in Figs. 10 and 1 1.

For example, by supposing to have a substrate with a dopant surface concentration equal to 4 10 atoms/cm' and if a porosity of about 58% is wanted to be obtained, from Fig. 11 curve 305 a pair of probable values of current density 9

(about 2 mA/cm and about 160 mA cm ) to be applied in this constant current step will be determined.

In case there are several values of current density to work with to obtain a determined percentage of porosity of porous silicon, as in the above-mentioned example, a first preferable choice is to utilize the lowest current density, in order to obtain a better homogeneity of porous silicon. In fact, experiments have disclosed that the porous layer is more homogeneous when a lower cuπent density is utilized during anodization. This is due to the fact that, being reaction kinetics slower under these conditions, pores are uniformly formed over the whole substrate. However, should conditions require, a likewise preferable choice can be the utilization of highest current density, in order to shorten the anodization process time.

Then, by multiplying the value of the so-determined current density times the heavily doped surface exposed to electrolytic solution, the current value to be applied in this first step will be obtained.

An alternative process to determine current density makes use of diagrams like those shown in Fig. 10, which represent the porosity dependency on the concentration of the electrolytic solution and current density for a fixed value of dopant concentration in the ^ silicon layer exposed to the solution.

For a very good result in the anodization and oxidation steps described hereinafter, the porosity of porous silicon will have to be between 50% and 60%. The oxidation step subsequent to the anodization step in fact takes place with an increase in volume of porous silicon columnar structures. It has been noted that that if porosity is greater than 60% the final oxide is porous and little massive. Viceversa, if porosity is lower than 50%o, the subsequent transformation into oxide involves formation of mechanical stress worsening the quality of the oxide itself and consequently of the wafer.

The following Figs. 12A and 12B represent exemplary variation in time of the anodization inventive process for some current values and for 4-inch wafer. In particular, Fig. 12A represents three different voltage variation (V on y-axis) in terms of time (minutes on x-axis), whereas Fig. 12B represents corresponding current variation (mA on y-axis) in terms of time (minutes on x-axis). The three different pair of variation have been designated with pair of Greek letters (α), (β) and (γ), respectively.

By way of example curves (β) will be followed and initial current to be utilized in the first step of the anodization process (step designated with I in the Figures) will be supposed to be equal to the value designated in Fig. 12B with the numeral 31 1 , that is 300 mA. By referring to curve (β) of Fig. 12 A, the potential variation is designated with 309. c when the anodization process is functioning with constant current. It can be noted that in time tl curve 309.C reaches a minimum value. In this time tl the second step of the anodization process, that is the constant voltage step, designated with II in the Figures, will start. The constant voltage value will be equal to the minimum value of curve 309. c of Fig. 12A, as it can be noted from part 309. a of curve (β) of Fig. 12A. During this second step, the current variation in terms of time will be decreasing- type, as shown by part 309.b of curve

(β) of Fig. 12B.

The second step of the anodization process will end as soon as the variation of curve (β) of Fig. 12B will stabilize about a minimum value. By referring to Figs.

12A and 12B, this minimum value is reached in time t2. In this time the anodization process will end, since all the ]NP⁺⁾ silicon of regions 104 and 107 will have been transformed into porous silicon.

Therefore, in step I the current is held constant at a determined value, for example a value such as to form porous silicon with a porosity between 50% and 60%). This step allows identifying the potential value to be applied in the following step. In this first step, according to the electrolyte composition and the dopant concentration of the N⁺⁽⁺⁾ silicon layer exposed to the solution, the current density could be chosen in the range between 0.5 and 300 mA/cm² (see Figs. 10 and 11).

In step II voltage is held constant at the above-determined value and current decreases. The value of the voltage determined in step I and subsequently applied to step

II depends on potential fall at the ends of electrodes of electrochemical cell which in turn depends on several factors such as kind of electrochemical solution, wafer resistivity, electrode sizes, etc. An indicative range may include values between 1 and 100 V. When current stabilizes (step III) all the N⁺⁽⁺⁾ silicon will have been converted into porous silicon and the anodization process will end.

Determining the time of switching time tl can take place in several ways. Usually, voltage is read at regular intervals, by making then easy determining the time in which it increases. The switching between step I and step II can take then place when voltage has increased by 2%, preferably no more than 5%, compared to the minimum thereof. A different mode consists in determining the voltage derivative and switching as soon this derivative changes in sign.

Determining time t2 (and therefore the end of the constant voltage step) takes place as soon as current stops varying inside a prefixed percentage, 5-10% for example.

The process can be clearly automatized by monitoring voltage and current values with specific sensors and with a circuitry if necessary connected to a computer for switching between the two operating modes (constant current/constant voltage).

It is to be noted that the so far described two-step process singularity allows an easy determination of the fact that all the silicon inside the regions 104, 107 has transformed into porous silicon. The voltage applied during the constant voltage step is so as not to allow the transformation of the less doped layer. Furthermore, since current density detects the transformation reaction of silicon into porous silicon, as above illustrated, when it reaches non-significant values it signals in this way the end of the reaction and therefore of the transformation of silicon into porous silicon.

By now referring to Fig. 8, this shows the wafer structure starting from time t2. The regions 104 and 107 referred to in the preceding Figs. 5, 6 and 7 are transformed into regions 110 of porous silicon with a prefixed value of porosity.

The oxidation process of the layer 110 will start now. This process is preferably performed in three steps.

A first step provides the stabilization of the porous silicon structure. This stabilization is performed at low temperature (about 300°C) for about 1 hour, in dry oxygen ambient; a second step provides the porous silicon oxidation at about 850°C and about 20 atmospheres in water vapour ambient; and a third steps aims at increasing the oxidized porous silicon density, and is performed in dry oxygen ambient at about 1200 °C. The structure of Fig. 9 is so obtained, comprising the oxide layers 111, correspondent to the preceding N⁺⁽⁺-⁾ layers 104 and 107.

A SOI structure without mechanical stress is so formed, wherein the porous silicon underneath the silicon islands is fully oxidized.

The obtained insulating layer has a resistivity of 10¹⁶ Ohm-cm, a fixed charge

10 ■ • density of about 1 10 cm^" . The silicon island above the insulating layer has preferably a maximum width of 40 μm and a defect density lower than 100 cm^"2.

A thin oxide layer, designated with 112, will have been formed on the sidewalls of the silicon islands 108. The oxidation of the surface of the layer 108 is avoided thanks to the mask 109, which is not represented in Fig. 9, since it has been removed at the end of the oxidation process.

The table in Fig. 13 shows, by way of example, some of the obtained buried oxide features. In this table dsιo designates the oxide thickness, C_ox designates the oxide capacity, N_sub designates the doping concentration at the interface between the regions 11 1 and 101, ε_r designates the dielectric constant of the layer 1 1 1 and, at last, p designates the resistivity of the layer 111.

A further embodiment of the present invention may provide that the structure of Fig. 14 is utilized as starting substrate, wherein there is a substrate comprising a N^ heavily doped single-crystal silicon wafer designated with numeral 200 whereon a thick single-crystal silicon layer designated with numeral 201 is deposited by epitaxial way. The following steps represented in Figs. 15, 16, 17, 18, 19, 20, 21 and 22 are respectively equivalent to the steps represented in Figs. 2, 3, 4, 5, 6, 7, 8 and 9. In the Figs. 15 to 22 the same numeration of the Figs. 2 to 9 has been maintained except for an additive constant equal to 100.

The present invention has been so far described according to the embodiments thereof illustrated by way of example and not for limitative purposes. It is to be meant that other embodiments may be provided, all comprised within the scope of the same invention as defined in the annexed claims.

Claims

CLALMS

1. A process for the selective anodization of one or more regions of of N⁺⁽⁺⁾ semiconducting material, for forming porous silicon, inside Φ/N⁺⁽⁺⁾/N^(")-type structures for semiconductor integrated circuits, characterized in that it comprises the steps of: performing a first step of constant cuπent anodization, by determining the value of a working voltage during this constant current anodization; and performing a second step of constant voltage anodization, the value of said constant voltage being equal to the working voltage value determined in the constant current anodization step

2. A selective anodization process according to claim 1, characterized in that the value of said constant current of the first step of constant current anodization is obtained from a working current density value determined based upon a desired porosity percentage of porous silicon.

3. A selective anodization process according to claim 1 or claim 2, characterized in that said desired porosity percentage of porous silicon is in the range of 50%-60%.

4. A selective anodization process according to claim 2 or claim 3, if depending from claim 2, characterized in that whenever the working current density values determined based upon said desired porosity percentage of porous silicon are more than one, the current value utilized in said constant current anodization step is obtained starting from the smallest value of said working current density values.

5. A selective anodization process according to claim 2 or claim 3, if depending from claim 2, characterized in that whenever the working current density values determined based upon said desired porosity percentage of porous silicon are more than one, the current value utilized in said constant current anodization step is obtained starting from the biggest value of said working current density values.

6. A selective anodization process according to any of the preceding claims, characterized in that said working voltage determined in said constant current anodization step is equal to the minimum value shown by the anodization voltage during said constant current anodization step.

7. A process for manufacturing FIPOS structures based upon the selective anodization of one or more regions of N⁺⁽⁺⁾ semiconducting material, for forming porous silicon, inside Φ/N⁺⁽⁺⁾/N^("-⁾-type structures for semiconductor integrated circuits and based upon the subsequent oxidation of said porous silicon, characterized in that said selective anodization is performed by the process according to any of the claims 1 to 6.

8. A process for manufacturing FIPOS structures according to claim 7, characterized in that said subsequent oxidation of said porous silicon comprises the steps of: stabilizing said porous silicon at a temperature of about 300 °C for about one hour, in dry oxygen ambient; oxidizing said porous silicon at about 850°C and about 20 atmospheres in water vapour; and increasing the density of the porous silicon oxidized in dry oxygen ambient at about 1200°C.

9. A FIPOS structure obtained by means of the process according to claim 7 or claim 8.8