FR2564241B1 - METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS - Google Patents

METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS

Info

Publication number
FR2564241B1
FR2564241B1 FR8407138A FR8407138A FR2564241B1 FR 2564241 B1 FR2564241 B1 FR 2564241B1 FR 8407138 A FR8407138 A FR 8407138A FR 8407138 A FR8407138 A FR 8407138A FR 2564241 B1 FR2564241 B1 FR 2564241B1
Authority
FR
France
Prior art keywords
integrated circuits
manufacturing silicon
insulator integrated
insulator
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8407138A
Other languages
French (fr)
Other versions
FR2564241A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to FR8407138A priority Critical patent/FR2564241B1/en
Publication of FR2564241A1 publication Critical patent/FR2564241A1/en
Application granted granted Critical
Publication of FR2564241B1 publication Critical patent/FR2564241B1/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
FR8407138A 1984-05-09 1984-05-09 METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS Expired FR2564241B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8407138A FR2564241B1 (en) 1984-05-09 1984-05-09 METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8407138A FR2564241B1 (en) 1984-05-09 1984-05-09 METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS

Publications (2)

Publication Number Publication Date
FR2564241A1 FR2564241A1 (en) 1985-11-15
FR2564241B1 true FR2564241B1 (en) 1987-03-27

Family

ID=9303792

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8407138A Expired FR2564241B1 (en) 1984-05-09 1984-05-09 METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS

Country Status (1)

Country Link
FR (1) FR2564241B1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0226091A3 (en) * 1985-12-17 1989-09-13 Texas Instruments Incorporated Semiconductor isolation using trenches and oxidation of anodized silicon sublayer
US5057450A (en) * 1991-04-01 1991-10-15 International Business Machines Corporation Method for fabricating silicon-on-insulator structures
FR2716748B1 (en) * 1994-02-25 1996-06-07 France Telecom Upholstery or filling process by gas phase deposition of a relief structure and application of this process for the manufacture of semiconductor elements.
IT1306182B1 (en) * 1999-08-02 2001-05-30 Shine Spa PROCEDURE FOR THE SELECTIVE ANODIZATION IN TWO PHASES OF A SEMICONDUCTIVE STRATOD FOR THE FORMATION OF POROUS SILICON.
IT1306183B1 (en) * 1999-08-02 2001-05-30 Shine Spa PROCEDURE FOR THE FORMATION OF THICKNESS INSULATING LAYERS PREPARED IN WAFER OF SEMICONDUCTORS FOR THE PRODUCTION OF
IT1306181B1 (en) * 1999-08-02 2001-05-30 Shine Spa PROCEDURE FOR THE FORMATION OF STRUCTURES OF DIFFERENT CONDUCTIVITY PRESENTING A HYPERFINE TRANSITION REGION, FOR THE PURPOSES OF
EP1113492B9 (en) * 1999-12-31 2010-02-03 STMicroelectronics S.r.l. Method for manufacturimg a SOI wafer
EP1294018A1 (en) * 2001-09-17 2003-03-19 Infineon Technologies AG Silicon on insulator substrate and method for manufacturing said substrate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104090A (en) * 1977-02-24 1978-08-01 International Business Machines Corporation Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation
US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
US4180416A (en) * 1978-09-27 1979-12-25 International Business Machines Corporation Thermal migration-porous silicon technique for forming deep dielectric isolation

Also Published As

Publication number Publication date
FR2564241A1 (en) 1985-11-15

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Legal Events

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ST Notification of lapse
ST Notification of lapse