IT1306181B1 - PROCEDURE FOR THE FORMATION OF STRUCTURES OF DIFFERENT CONDUCTIVITY PRESENTING A HYPERFINE TRANSITION REGION, FOR THE PURPOSES OF - Google Patents

PROCEDURE FOR THE FORMATION OF STRUCTURES OF DIFFERENT CONDUCTIVITY PRESENTING A HYPERFINE TRANSITION REGION, FOR THE PURPOSES OF

Info

Publication number
IT1306181B1
IT1306181B1 IT1999RM000496A ITRM990496A IT1306181B1 IT 1306181 B1 IT1306181 B1 IT 1306181B1 IT 1999RM000496 A IT1999RM000496 A IT 1999RM000496A IT RM990496 A ITRM990496 A IT RM990496A IT 1306181 B1 IT1306181 B1 IT 1306181B1
Authority
IT
Italy
Prior art keywords
presenting
procedure
purposes
structures
formation
Prior art date
Application number
IT1999RM000496A
Other languages
Italian (it)
Inventor
Marco Balucani
Vitaly Bondarenko
Leonid Dolgyi
Aldo Ferrari
Giulio Lamedica
Valentina Yakovtseva
Original Assignee
Shine Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shine Spa filed Critical Shine Spa
Priority to IT1999RM000496A priority Critical patent/IT1306181B1/en
Publication of ITRM990496A0 publication Critical patent/ITRM990496A0/en
Priority to PCT/IT2000/000329 priority patent/WO2001009942A1/en
Priority to AU67237/00A priority patent/AU6723700A/en
Publication of ITRM990496A1 publication Critical patent/ITRM990496A1/en
Application granted granted Critical
Publication of IT1306181B1 publication Critical patent/IT1306181B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/2205—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Element Separation (AREA)
IT1999RM000496A 1999-08-02 1999-08-02 PROCEDURE FOR THE FORMATION OF STRUCTURES OF DIFFERENT CONDUCTIVITY PRESENTING A HYPERFINE TRANSITION REGION, FOR THE PURPOSES OF IT1306181B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT1999RM000496A IT1306181B1 (en) 1999-08-02 1999-08-02 PROCEDURE FOR THE FORMATION OF STRUCTURES OF DIFFERENT CONDUCTIVITY PRESENTING A HYPERFINE TRANSITION REGION, FOR THE PURPOSES OF
PCT/IT2000/000329 WO2001009942A1 (en) 1999-08-02 2000-08-02 Process for forming structure with different doped regions, showing a hyperfine transition region, for forming porous silicon
AU67237/00A AU6723700A (en) 1999-08-02 2000-08-02 Process for forming structure with different doped regions, showing a hyperfine transition region, for forming porous silicon

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1999RM000496A IT1306181B1 (en) 1999-08-02 1999-08-02 PROCEDURE FOR THE FORMATION OF STRUCTURES OF DIFFERENT CONDUCTIVITY PRESENTING A HYPERFINE TRANSITION REGION, FOR THE PURPOSES OF

Publications (3)

Publication Number Publication Date
ITRM990496A0 ITRM990496A0 (en) 1999-08-02
ITRM990496A1 ITRM990496A1 (en) 2001-02-02
IT1306181B1 true IT1306181B1 (en) 2001-05-30

Family

ID=11406920

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1999RM000496A IT1306181B1 (en) 1999-08-02 1999-08-02 PROCEDURE FOR THE FORMATION OF STRUCTURES OF DIFFERENT CONDUCTIVITY PRESENTING A HYPERFINE TRANSITION REGION, FOR THE PURPOSES OF

Country Status (3)

Country Link
AU (1) AU6723700A (en)
IT (1) IT1306181B1 (en)
WO (1) WO2001009942A1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2564241B1 (en) * 1984-05-09 1987-03-27 Bois Daniel METHOD FOR MANUFACTURING SILICON-ON-INSULATOR INTEGRATED CIRCUITS
EP0226091A3 (en) * 1985-12-17 1989-09-13 Texas Instruments Incorporated Semiconductor isolation using trenches and oxidation of anodized silicon sublayer
JPH01161826A (en) * 1987-12-18 1989-06-26 Toshiba Corp Vapor phase epitaxial growth method
JPH0714840B2 (en) * 1988-10-18 1995-02-22 インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン Epitaxial film growth method
US4910165A (en) * 1988-11-04 1990-03-20 Ncr Corporation Method for forming epitaxial silicon on insulator structures using oxidized porous silicon
DE19501838A1 (en) * 1995-01-21 1996-07-25 Telefunken Microelectron Prodn. of silicon-on-insulator structures

Also Published As

Publication number Publication date
WO2001009942A1 (en) 2001-02-08
ITRM990496A1 (en) 2001-02-02
AU6723700A (en) 2001-02-19
ITRM990496A0 (en) 1999-08-02

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