IT1293041B1 - Dispositivo di memoria a celle multilivello a transistor a gate fluttuante e metodo di programmazione e stabilizzazione della carica - Google Patents

Dispositivo di memoria a celle multilivello a transistor a gate fluttuante e metodo di programmazione e stabilizzazione della carica

Info

Publication number
IT1293041B1
IT1293041B1 IT97RM000344A ITRM970344A IT1293041B1 IT 1293041 B1 IT1293041 B1 IT 1293041B1 IT 97RM000344 A IT97RM000344 A IT 97RM000344A IT RM970344 A ITRM970344 A IT RM970344A IT 1293041 B1 IT1293041 B1 IT 1293041B1
Authority
IT
Italy
Prior art keywords
memory device
floating gate
gate transistor
stabilization method
cell memory
Prior art date
Application number
IT97RM000344A
Other languages
English (en)
Italian (it)
Inventor
Zenzo Maurizio Di
Giuliano Imondi
Giulio Marotta
Giuseppe Savarese
Original Assignee
Consorzio Eagle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consorzio Eagle filed Critical Consorzio Eagle
Priority to IT97RM000344A priority Critical patent/IT1293041B1/it
Publication of ITRM970344A0 publication Critical patent/ITRM970344A0/it
Publication of ITRM970344A1 publication Critical patent/ITRM970344A1/it
Application granted granted Critical
Publication of IT1293041B1 publication Critical patent/IT1293041B1/it

Links

IT97RM000344A 1997-06-09 1997-06-09 Dispositivo di memoria a celle multilivello a transistor a gate fluttuante e metodo di programmazione e stabilizzazione della carica IT1293041B1 (it)

Priority Applications (1)

Application Number Priority Date Filing Date Title
IT97RM000344A IT1293041B1 (it) 1997-06-09 1997-06-09 Dispositivo di memoria a celle multilivello a transistor a gate fluttuante e metodo di programmazione e stabilizzazione della carica

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT97RM000344A IT1293041B1 (it) 1997-06-09 1997-06-09 Dispositivo di memoria a celle multilivello a transistor a gate fluttuante e metodo di programmazione e stabilizzazione della carica

Publications (3)

Publication Number Publication Date
ITRM970344A0 ITRM970344A0 (enrdf_load_stackoverflow) 1997-06-09
ITRM970344A1 ITRM970344A1 (it) 1998-12-09
IT1293041B1 true IT1293041B1 (it) 1999-02-11

Family

ID=11405121

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97RM000344A IT1293041B1 (it) 1997-06-09 1997-06-09 Dispositivo di memoria a celle multilivello a transistor a gate fluttuante e metodo di programmazione e stabilizzazione della carica

Country Status (1)

Country Link
IT (1) IT1293041B1 (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
ITRM970344A0 (enrdf_load_stackoverflow) 1997-06-09
ITRM970344A1 (it) 1998-12-09

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