IT1283363B1 - Rete a ritardo asimmetrico e impulsivo e relativo generatore di impulsi costanti - Google Patents

Rete a ritardo asimmetrico e impulsivo e relativo generatore di impulsi costanti

Info

Publication number
IT1283363B1
IT1283363B1 IT96MI001626A ITMI961626A IT1283363B1 IT 1283363 B1 IT1283363 B1 IT 1283363B1 IT 96MI001626 A IT96MI001626 A IT 96MI001626A IT MI961626 A ITMI961626 A IT MI961626A IT 1283363 B1 IT1283363 B1 IT 1283363B1
Authority
IT
Italy
Prior art keywords
pulsive
asymmetric
pulse generator
delay network
constant pulse
Prior art date
Application number
IT96MI001626A
Other languages
English (en)
Inventor
Luigi Pascucci
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT96MI001626A priority Critical patent/IT1283363B1/it
Publication of ITMI961626A0 publication Critical patent/ITMI961626A0/it
Priority to US08/900,424 priority patent/US6046619A/en
Publication of ITMI961626A1 publication Critical patent/ITMI961626A1/it
Application granted granted Critical
Publication of IT1283363B1 publication Critical patent/IT1283363B1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00293—Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Pulse Circuits (AREA)
IT96MI001626A 1996-07-30 1996-07-30 Rete a ritardo asimmetrico e impulsivo e relativo generatore di impulsi costanti IT1283363B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT96MI001626A IT1283363B1 (it) 1996-07-30 1996-07-30 Rete a ritardo asimmetrico e impulsivo e relativo generatore di impulsi costanti
US08/900,424 US6046619A (en) 1996-07-30 1997-07-25 Asymmetrical pulsive delay network

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT96MI001626A IT1283363B1 (it) 1996-07-30 1996-07-30 Rete a ritardo asimmetrico e impulsivo e relativo generatore di impulsi costanti

Publications (3)

Publication Number Publication Date
ITMI961626A0 ITMI961626A0 (it) 1996-07-30
ITMI961626A1 ITMI961626A1 (it) 1998-01-30
IT1283363B1 true IT1283363B1 (it) 1998-04-17

Family

ID=11374707

Family Applications (1)

Application Number Title Priority Date Filing Date
IT96MI001626A IT1283363B1 (it) 1996-07-30 1996-07-30 Rete a ritardo asimmetrico e impulsivo e relativo generatore di impulsi costanti

Country Status (2)

Country Link
US (1) US6046619A (it)
IT (1) IT1283363B1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9671284B1 (en) * 2016-01-14 2017-06-06 Kiskeya Microsystems Llc Single-photon avalanche diode circuit with variable hold-off time and dual delay regime
US11264974B2 (en) * 2020-03-18 2022-03-01 Mediatek Inc. Processing circuit using delay element coupled between control terminal and connection terminal of input transistor for hold time violation immunity
CN114374377A (zh) * 2022-01-11 2022-04-19 长鑫存储技术有限公司 延时电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4843265A (en) * 1986-02-10 1989-06-27 Dallas Semiconductor Corporation Temperature compensated monolithic delay circuit
US5130582A (en) * 1989-09-19 1992-07-14 Tdk Corporation Delay circuit which is free from temperature variation, power supply voltage variation and process variation
US5300837A (en) * 1992-09-17 1994-04-05 At&T Bell Laboratories Delay compensation technique for buffers
FR2699023B1 (fr) * 1992-12-09 1995-02-24 Texas Instruments France Circuit à retard commandé.

Also Published As

Publication number Publication date
ITMI961626A0 (it) 1996-07-30
ITMI961626A1 (it) 1998-01-30
US6046619A (en) 2000-04-04

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Legal Events

Date Code Title Description
0001 Granted