IT1266450B1 - Mini-memoria cache per memorie di campo. - Google Patents

Mini-memoria cache per memorie di campo.

Info

Publication number
IT1266450B1
IT1266450B1 IT93RM000810A ITRM930810A IT1266450B1 IT 1266450 B1 IT1266450 B1 IT 1266450B1 IT 93RM000810 A IT93RM000810 A IT 93RM000810A IT RM930810 A ITRM930810 A IT RM930810A IT 1266450 B1 IT1266450 B1 IT 1266450B1
Authority
IT
Italy
Prior art keywords
cache memory
miniature
field memories
data
pipeline
Prior art date
Application number
IT93RM000810A
Other languages
English (en)
Inventor
Giuliano Imondi
Stefano Menichelli
Carlo Sansone
Original Assignee
Texas Instruments Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Italia Spa filed Critical Texas Instruments Italia Spa
Priority to IT93RM000810A priority Critical patent/IT1266450B1/it
Publication of ITRM930810A0 publication Critical patent/ITRM930810A0/it
Priority to JP7515976A priority patent/JPH09509002A/ja
Priority to US08/663,063 priority patent/US6005820A/en
Priority to PCT/EP1994/004071 priority patent/WO1995016266A1/en
Priority to KR1019960702892A priority patent/KR100362341B1/ko
Priority to DE69423113T priority patent/DE69423113T2/de
Priority to EP95902133A priority patent/EP0733259B1/en
Publication of ITRM930810A1 publication Critical patent/ITRM930810A1/it
Application granted granted Critical
Publication of IT1266450B1 publication Critical patent/IT1266450B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Dram (AREA)

Abstract

Oggetto dell'invenzione è una memoria di servizio o cache per i dati da associare ad una pipeline, comprendente un registro in serie per scrittura disposto in modo da ricevere i dati di ingresso simultaneamente con l'uscita dei dati da detta pipeline.
IT93RM000810A 1993-12-07 1993-12-07 Mini-memoria cache per memorie di campo. IT1266450B1 (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT93RM000810A IT1266450B1 (it) 1993-12-07 1993-12-07 Mini-memoria cache per memorie di campo.
JP7515976A JPH09509002A (ja) 1993-12-07 1994-12-07 フィールドメモリおよび関連技術の改善
US08/663,063 US6005820A (en) 1993-12-07 1994-12-07 Field memories
PCT/EP1994/004071 WO1995016266A1 (en) 1993-12-07 1994-12-07 Improvements in or relating to field memories
KR1019960702892A KR100362341B1 (ko) 1993-12-07 1994-12-07 개선된필드메모리
DE69423113T DE69423113T2 (de) 1993-12-07 1994-12-07 Verbesserter feldspeicher
EP95902133A EP0733259B1 (en) 1993-12-07 1994-12-07 Improved field memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT93RM000810A IT1266450B1 (it) 1993-12-07 1993-12-07 Mini-memoria cache per memorie di campo.

Publications (3)

Publication Number Publication Date
ITRM930810A0 ITRM930810A0 (it) 1993-12-07
ITRM930810A1 ITRM930810A1 (it) 1995-06-07
IT1266450B1 true IT1266450B1 (it) 1996-12-30

Family

ID=11402086

Family Applications (1)

Application Number Title Priority Date Filing Date
IT93RM000810A IT1266450B1 (it) 1993-12-07 1993-12-07 Mini-memoria cache per memorie di campo.

Country Status (2)

Country Link
US (1) US6005820A (it)
IT (1) IT1266450B1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002109878A (ja) * 2000-09-29 2002-04-12 Oki Electric Ind Co Ltd シリアルアクセスメモリ
US7215585B2 (en) * 2005-09-01 2007-05-08 Micron Technology, Inc. Method and apparatus for synchronizing data from memory arrays

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3623020A (en) * 1969-12-08 1971-11-23 Rca Corp First-in first-out buffer register
US3898632A (en) * 1974-07-15 1975-08-05 Sperry Rand Corp Semiconductor block-oriented read/write memory
US3967251A (en) * 1975-04-17 1976-06-29 Xerox Corporation User variable computer memory module
JPS56137581A (en) * 1980-03-28 1981-10-27 Toshiba Corp Random access memory circuit
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory
JPS63282997A (ja) * 1987-05-15 1988-11-18 Mitsubishi Electric Corp ブロツクアクセスメモリ
US5200925A (en) * 1988-07-29 1993-04-06 Mitsubishi Denki Kabushiki Kaisha Serial access semiconductor memory device and operating method therefor
DE3832328A1 (de) * 1988-09-23 1990-03-29 Broadcast Television Syst Speicheranordnung fuer digitale signale
JPH0547173A (ja) * 1991-08-09 1993-02-26 Mitsubishi Electric Corp ダイナミツク型半導体記憶装置および画像データ発生装置
JPH0798979A (ja) * 1993-09-29 1995-04-11 Toshiba Corp 半導体記憶装置
US5537346A (en) * 1994-05-20 1996-07-16 Samsung Electronics Co., Ltd. Semiconductor memory device obtaining high bandwidth and signal line layout method thereof

Also Published As

Publication number Publication date
US6005820A (en) 1999-12-21
ITRM930810A1 (it) 1995-06-07
ITRM930810A0 (it) 1993-12-07

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961016