IT1263811B - Microprocessore con dispositivo per l'esecuzione parallela di istruzioni - Google Patents
Microprocessore con dispositivo per l'esecuzione parallela di istruzioniInfo
- Publication number
- IT1263811B IT1263811B ITMI930109A ITMI930109A IT1263811B IT 1263811 B IT1263811 B IT 1263811B IT MI930109 A ITMI930109 A IT MI930109A IT MI930109 A ITMI930109 A IT MI930109A IT 1263811 B IT1263811 B IT 1263811B
- Authority
- IT
- Italy
- Prior art keywords
- instructions
- instruction
- register
- parallel
- pipelines
- Prior art date
Links
- 230000009977 dual effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/3822—Parallel decoding, e.g. parallel decode units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
Un sistema informatico comprende un decodificatore di doppia istruzione che emette due istruzioni in parallelo in un singolo ciclo d'orologio se non vi sono dipendenze di registri fra le istruzioni e le istruzioni rientrano in un predeterminato sottoinsieme dell'insieme completo di istruzioni. Il sistema comprende pipeline di istruzioni primo e secondo. Il primo pipeline esegue un'istruzione emessa dall'insieme completo di istruzioni, mentre il secondo pipeline esegue solo un predeterminato sottoinsieme di istruzioni scelto sulla base di principi di località. Un dispositivo di verifica di dipendenze di registri determina se il registro di destinazione di una prima istruzione viene usato durante l'esecuzione di una seconda istruzione in una sequenza di istruzioni.Quando entrambe le istruzioni sono nel sottoinsieme e non vi sono dipendenze, le istruzioni prima e seconda possono essere emesse in parallelo nei pipeline primo e secondo.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US82388192A | 1992-01-23 | 1992-01-23 |
Publications (3)
Publication Number | Publication Date |
---|---|
ITMI930109A0 ITMI930109A0 (it) | 1993-01-25 |
ITMI930109A1 ITMI930109A1 (it) | 1994-07-25 |
IT1263811B true IT1263811B (it) | 1996-09-03 |
Family
ID=25239997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITMI930109A IT1263811B (it) | 1992-01-23 | 1993-01-25 | Microprocessore con dispositivo per l'esecuzione parallela di istruzioni |
Country Status (8)
Country | Link |
---|---|
US (1) | US5475824A (it) |
JP (1) | JPH0628185A (it) |
CN (1) | CN1074771A (it) |
DE (1) | DE4301417C2 (it) |
FR (1) | FR2686717A1 (it) |
GB (1) | GB2263565B (it) |
HK (1) | HK1006882A1 (it) |
IT (1) | IT1263811B (it) |
Families Citing this family (43)
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CA2123442A1 (en) * | 1993-09-20 | 1995-03-21 | David S. Ray | Multiple execution unit dispatch with instruction dependency |
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EP0649085B1 (en) * | 1993-10-18 | 1998-03-04 | Cyrix Corporation | Microprocessor pipe control and register translation |
US5630149A (en) * | 1993-10-18 | 1997-05-13 | Cyrix Corporation | Pipelined processor with register renaming hardware to accommodate multiple size registers |
US6138230A (en) * | 1993-10-18 | 2000-10-24 | Via-Cyrix, Inc. | Processor with multiple execution pipelines using pipe stage state information to control independent movement of instructions between pipe stages of an execution pipeline |
GB2289354B (en) * | 1994-05-03 | 1997-08-27 | Advanced Risc Mach Ltd | Multiple instruction set mapping |
GB2290395B (en) | 1994-06-10 | 1997-05-28 | Advanced Risc Mach Ltd | Interoperability with multiple instruction sets |
US5692151A (en) * | 1994-11-14 | 1997-11-25 | International Business Machines Corporation | High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address |
US5931941A (en) * | 1995-04-28 | 1999-08-03 | Lsi Logic Corporation | Interface for a modularized computational unit to a CPU |
US5790826A (en) * | 1996-03-19 | 1998-08-04 | S3 Incorporated | Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes |
US6212601B1 (en) * | 1996-08-30 | 2001-04-03 | Texas Instruments Incorporated | Microprocessor system with block move circuit disposed between cache circuits |
JP4226085B2 (ja) * | 1996-10-31 | 2009-02-18 | 株式会社ルネサステクノロジ | マイクロプロセッサ及びマルチプロセッサシステム |
KR100231852B1 (ko) * | 1996-11-06 | 1999-12-01 | 김영환 | 듀얼 파이프라인 프로세서에서 로드 명령의 병렬 수행 장치 |
US5802386A (en) * | 1996-11-19 | 1998-09-01 | International Business Machines Corporation | Latency-based scheduling of instructions in a superscalar processor |
US5974538A (en) * | 1997-02-21 | 1999-10-26 | Wilmot, Ii; Richard Byron | Method and apparatus for annotating operands in a computer system with source instruction identifiers |
GB2325535A (en) * | 1997-05-23 | 1998-11-25 | Aspex Microsystems Ltd | Data processor controller with accelerated instruction generation |
JPH11134197A (ja) * | 1997-10-29 | 1999-05-21 | Fujitsu Ltd | Vliw方式計算機用のコンパイル装置及び方法並びにコンパイル実行プログラムを格納した記録媒体 |
US6029267A (en) * | 1997-11-25 | 2000-02-22 | Lucent Technologies Inc. | Single-cycle, soft decision, compare-select operation using dual-add processor |
US6076154A (en) * | 1998-01-16 | 2000-06-13 | U.S. Philips Corporation | VLIW processor has different functional units operating on commands of different widths |
US6237101B1 (en) | 1998-08-03 | 2001-05-22 | International Business Machines Corporation | Microprocessor including controller for reduced power consumption and method therefor |
JP2000305781A (ja) * | 1999-04-21 | 2000-11-02 | Mitsubishi Electric Corp | Vliw方式プロセッサ、コード圧縮装置、コード圧縮方法およびコード圧縮プログラムを記録した媒体 |
US6330657B1 (en) * | 1999-05-18 | 2001-12-11 | Ip-First, L.L.C. | Pairing of micro instructions in the instruction queue |
US6453412B1 (en) * | 1999-07-20 | 2002-09-17 | Ip First L.L.C. | Method and apparatus for reissuing paired MMX instructions singly during exception handling |
US6839833B1 (en) * | 1999-10-15 | 2005-01-04 | Unisys Corporation | Pipeline depth controller for an instruction processor |
GB2359641B (en) * | 2000-02-25 | 2002-02-13 | Siroyan Ltd | Mapping circuitry and method |
US6748411B1 (en) | 2000-11-20 | 2004-06-08 | Agere Systems Inc. | Hierarchical carry-select multiple-input split adder |
US7711926B2 (en) * | 2001-04-18 | 2010-05-04 | Mips Technologies, Inc. | Mapping system and method for instruction set processing |
US7363467B2 (en) * | 2002-01-03 | 2008-04-22 | Intel Corporation | Dependence-chain processing using trace descriptors having dependency descriptors |
US7111125B2 (en) * | 2002-04-02 | 2006-09-19 | Ip-First, Llc | Apparatus and method for renaming a data block within a cache |
US7398372B2 (en) * | 2002-06-25 | 2008-07-08 | Intel Corporation | Fusing load and alu operations |
US7051190B2 (en) * | 2002-06-25 | 2006-05-23 | Intel Corporation | Intra-instruction fusion |
JP3816844B2 (ja) * | 2002-07-05 | 2006-08-30 | 富士通株式会社 | プロセッサ及び命令制御方法 |
US7502910B2 (en) * | 2003-01-28 | 2009-03-10 | Sun Microsystems, Inc. | Sideband scout thread processor for reducing latency associated with a main processor |
US20060179275A1 (en) * | 2005-02-08 | 2006-08-10 | Takeshi Yamazaki | Methods and apparatus for processing instructions in a multi-processor system |
US20100115239A1 (en) * | 2008-10-29 | 2010-05-06 | Adapteva Incorporated | Variable instruction width digital signal processor |
JP2011008732A (ja) * | 2009-06-29 | 2011-01-13 | Fujitsu Ltd | プライオリティ回路、演算処理装置及び演算処理方法 |
US8914615B2 (en) | 2011-12-02 | 2014-12-16 | Arm Limited | Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format |
US10437596B2 (en) * | 2014-11-26 | 2019-10-08 | Texas Instruments Incorporated | Processor with a full instruction set decoder and a partial instruction set decoder |
US10514925B1 (en) * | 2016-01-28 | 2019-12-24 | Apple Inc. | Load speculation recovery |
CN109947479A (zh) * | 2019-01-29 | 2019-06-28 | 安谋科技(中国)有限公司 | 指令执行方法及其处理器、介质和系统 |
CN110780616A (zh) * | 2019-09-06 | 2020-02-11 | 重庆东渝中能实业有限公司 | 一种基于流水线技术处理通讯命令的方法 |
CN112579174B (zh) * | 2020-12-05 | 2023-01-31 | 西安翔腾微电子科技有限公司 | 一种多周期双发射指令可发射的检测电路及方法 |
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-
1993
- 1993-01-05 GB GB9300079A patent/GB2263565B/en not_active Expired - Lifetime
- 1993-01-20 DE DE4301417A patent/DE4301417C2/de not_active Expired - Lifetime
- 1993-01-21 CN CN93101139.6A patent/CN1074771A/zh active Pending
- 1993-01-21 FR FR9300580A patent/FR2686717A1/fr active Granted
- 1993-01-25 JP JP5027177A patent/JPH0628185A/ja active Pending
- 1993-01-25 IT ITMI930109A patent/IT1263811B/it active IP Right Grant
-
1995
- 1995-02-10 US US08/386,595 patent/US5475824A/en not_active Expired - Lifetime
-
1998
- 1998-06-22 HK HK98105913A patent/HK1006882A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
DE4301417C2 (de) | 1998-06-18 |
HK1006882A1 (en) | 1999-03-19 |
FR2686717A1 (fr) | 1993-07-30 |
GB2263565A (en) | 1993-07-28 |
GB2263565B (en) | 1995-08-30 |
US5475824A (en) | 1995-12-12 |
JPH0628185A (ja) | 1994-02-04 |
ITMI930109A1 (it) | 1994-07-25 |
GB9300079D0 (en) | 1993-03-03 |
ITMI930109A0 (it) | 1993-01-25 |
CN1074771A (zh) | 1993-07-28 |
DE4301417A1 (it) | 1993-07-29 |
FR2686717B1 (it) | 1995-03-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19990128 |