IT1229126B - Metodo e apparecchio per coerenza di prememoria. - Google Patents

Metodo e apparecchio per coerenza di prememoria.

Info

Publication number
IT1229126B
IT1229126B IT8919608A IT1960889A IT1229126B IT 1229126 B IT1229126 B IT 1229126B IT 8919608 A IT8919608 A IT 8919608A IT 1960889 A IT1960889 A IT 1960889A IT 1229126 B IT1229126 B IT 1229126B
Authority
IT
Italy
Prior art keywords
reminder
coherence
reminder coherence
Prior art date
Application number
IT8919608A
Other languages
English (en)
Other versions
IT8919608A0 (it
Inventor
Jon Rubinstein
Glen S Miranker
Original Assignee
Ardent Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ardent Computer Corp filed Critical Ardent Computer Corp
Publication of IT8919608A0 publication Critical patent/IT8919608A0/it
Application granted granted Critical
Publication of IT1229126B publication Critical patent/IT1229126B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
IT8919608A 1988-03-01 1989-03-01 Metodo e apparecchio per coerenza di prememoria. IT1229126B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16273788A 1988-03-01 1988-03-01

Publications (2)

Publication Number Publication Date
IT8919608A0 IT8919608A0 (it) 1989-03-01
IT1229126B true IT1229126B (it) 1991-07-22

Family

ID=22586939

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8919608A IT1229126B (it) 1988-03-01 1989-03-01 Metodo e apparecchio per coerenza di prememoria.

Country Status (3)

Country Link
JP (1) JPH0210462A (it)
GB (1) GB2216308A (it)
IT (1) IT1229126B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105677583B (zh) * 2015-12-31 2019-01-08 华为技术有限公司 一种缓存管理方法及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4167782A (en) * 1977-12-22 1979-09-11 Honeywell Information Systems Inc. Continuous updating of cache store
CA1159153A (en) * 1979-12-14 1983-12-20 Charles P. Ryan Apparatus for cache clearing
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4410944A (en) * 1981-03-24 1983-10-18 Burroughs Corporation Apparatus and method for maintaining cache memory integrity in a shared memory environment
DE3582506D1 (de) * 1984-02-10 1991-05-23 Prime Computer Inc Cache-kohaerenz-anordnung.
DE3740834A1 (de) * 1987-01-22 1988-08-04 Nat Semiconductor Corp Aufrechterhaltung der kohaerenz zwischen einem mikroprozessorenintegrierten cache-speicher und einem externen speicher

Also Published As

Publication number Publication date
JPH0210462A (ja) 1990-01-16
GB8903963D0 (en) 1989-04-05
GB2216308A (en) 1989-10-04
IT8919608A0 (it) 1989-03-01

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