GB8903963D0 - Cache consistency method and apparatus - Google Patents

Cache consistency method and apparatus

Info

Publication number
GB8903963D0
GB8903963D0 GB898903963A GB8903963A GB8903963D0 GB 8903963 D0 GB8903963 D0 GB 8903963D0 GB 898903963 A GB898903963 A GB 898903963A GB 8903963 A GB8903963 A GB 8903963A GB 8903963 D0 GB8903963 D0 GB 8903963D0
Authority
GB
United Kingdom
Prior art keywords
cache consistency
consistency method
cache
consistency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB898903963A
Other versions
GB2216308A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ardent Computer Corp
Original Assignee
Ardent Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ardent Computer Corp filed Critical Ardent Computer Corp
Publication of GB8903963D0 publication Critical patent/GB8903963D0/en
Publication of GB2216308A publication Critical patent/GB2216308A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
GB8903963A 1988-03-01 1989-02-22 Maintaining cache consistency Withdrawn GB2216308A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16273788A 1988-03-01 1988-03-01

Publications (2)

Publication Number Publication Date
GB8903963D0 true GB8903963D0 (en) 1989-04-05
GB2216308A GB2216308A (en) 1989-10-04

Family

ID=22586939

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8903963A Withdrawn GB2216308A (en) 1988-03-01 1989-02-22 Maintaining cache consistency

Country Status (3)

Country Link
JP (1) JPH0210462A (en)
GB (1) GB2216308A (en)
IT (1) IT1229126B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105677583B (en) * 2015-12-31 2019-01-08 华为技术有限公司 A kind of buffer memory management method and device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4167782A (en) * 1977-12-22 1979-09-11 Honeywell Information Systems Inc. Continuous updating of cache store
FR2472232B1 (en) * 1979-12-14 1988-04-22 Honeywell Inf Systems DEVICE AND METHOD FOR DELETING ANTEMEMORY
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4410944A (en) * 1981-03-24 1983-10-18 Burroughs Corporation Apparatus and method for maintaining cache memory integrity in a shared memory environment
ATE62764T1 (en) * 1984-02-10 1991-05-15 Prime Computer Inc CACHE COHERENCE ARRANGEMENT.
DE3740834A1 (en) * 1987-01-22 1988-08-04 Nat Semiconductor Corp MAINTAINING COHERENCE BETWEEN A MICROPROCESSOR-INTEGRATED CACHE AND AN EXTERNAL MEMORY

Also Published As

Publication number Publication date
JPH0210462A (en) 1990-01-16
IT1229126B (en) 1991-07-22
GB2216308A (en) 1989-10-04
IT8919608A0 (en) 1989-03-01

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Legal Events

Date Code Title Description
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)