JPH0210462A - Method of forcing cohesion of cash for computer apparatus and computer apparatus - Google Patents

Abstract

PURPOSE: To realize an efficient caching operation by invalidating a cache entry when the cache entry contradicts an entry in a main memory. CONSTITUTION: Processors 11-13 are mutually connected by a bus 10. The processors 11-13 have bus interface devices 14, bus watchers 15, data cache memories 18, processors 23 and floating point processors 30. The bus watcher 15 has an even address tag array 16 and an odd address tag array 17, monitors the bus 10 for write transaction, and invalidates the corresponding cache entry when write transaction is executed by a memory mutator.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention is in the field of methods and apparatus for enforcing cache coherency among multiple devices in a computer system.

[Background Art and Problems to be Solved by the Invention] In computer devices, cache memory can be used to improve the access speed of frequently used data and programs.

Cache memory is typically high-speed memory that is comparable to the speed of a CPU. That memory is CP
It acts as a buffer between U and the slower main memory. Typically, frequently used data is stored in cache memory and accessed by the KCPU during read operations. A write operation causes a write to υ cache memory and, at some point, to main memory. To update main memory from cache memory,
There are two methods: writing through the cache and writing back to the cache.

In a write-through-cache mechanism, a write to cache memory causes a corresponding write to main memory at approximately the same time.

In write-back to cache methods, main memory is updated with new data at times that are not necessarily correlated with writes to cache memory. An example of a write-back cache is described below in connection with a smart cache protocol.

In order to use cache memory, at some point the cache memory and main memory must correspond accurately. In the case of a single cpo device without a co-executor, this is a major problem. However, when several memory mudata (devices such as CPUs that can modify memory) share a memory, cache coherency becomes a major problem. For example, if the data is processor 1
is read into its cache memory by processor 2, and subsequently read into its cache memory by processor 2;
If the data is then updated to processor 1, processor 2 needs to update or invalidate its data version or the data will be inconsistent between processors 1 and 2.

Several methods are well known for enforcing cache coherency when multiple processors share one main memory and have separate cache memories. One method is to have software that enforces cache coherency. Typically, software algorithms that enforce cache coherency utilize time stamps on data in main memory and cache memory. Some software algorithms include using clock cycles to enforce cache coherency, increasing system software complexity, and adding the overhead of timestamps or similar marks to each block of data in memory. There are drawbacks.

The second method uses a bus protocol that attempts to keep all caches in the device consistent, rather than keeping track of all entries in the cache that are dirty (i.e., updated). uses the smart cache protocol. There may be only one tainted version of a particular device's data within the device. If a processor that does not have the dirty nine version attempts to read the data, the device must force a dirty copy to be written to main memory and then allow a second processor to read the data. It won't happen.

This introduces some operational complexity, such as the device knowing where each copy of the data is, and not allowing data to be read from the cache after a dirty version of the data exists. This will result in the enforcement of strict rules. Additionally, the use of multiple data buses and bus masters without caching adds complexity.

A third way to enforce cache coherency is to use a bus watcher on writes through the cache. Typically, a path watcher is associated with each CPU having a cache memory. The bus watcher is responsible for monitoring write transactions on the device bus and determining whether the write transactions update or invalidate data in its processor cache memory.

Additionally, in typical computer systems that utilize cache memory, it is advantageous to fetch multiple words from main memory in order to place multiple words from main memory into cache memory with a single fetch instruction. Such devices are typically advantageous in bus and memory management.

For example, instructions are typically accessed sequentially during program execution, and branch instructions are relatively unbiased compared to instructions that are executed sequentially. Therefore, fetching blocks of instructions makes the device efficient.

Device designs that allow seven etches of data blocks into cache are well known. However, with advances in microprocessors, control of cache memory has moved inside the microprocessor. In devices using such microprocessors, the microprocessor processes seven words one word at a time.
Having sex is normal. It would be desirable to develop methods and apparatus that allow the use of standard microprocessors in computing devices to perform efficient caching operations.

Furthermore, in computer equipment, it is known that when communicating between modules, a bus with a first bandwidth of, for example, 64 bits is used, and when communicating within a module, a bus with a second bandwidth, for example, 32 bits is used. It is being

In such computing devices, funneling data from a wider bandwidth bus onto a narrower bandwidth bus often causes the device to become clogged.

[Means to solve problems]

The present invention provides a computer device using a large number of memory data and at least one cache memory,
A method and apparatus for enforcing cache coherency is disclosed. In a preferred embodiment, each of the multiple microprocessor devices is coupled to a separate cache memory. The device also has other memory emulators such as I10 devices, graphics processors, and floating point processors without cache memory.

The preferred embodiment uses a write-mediated cache and a bus watcher mechanism that combines a path watcher with each cache memory. The bus watcher has even and odd address tag arrays. The even address tag array holds addresses of data in cache memory that correspond to even addresses in main memory. Similar K
, an odd address tag array holds addresses of data in cache memory that correspond to odd addresses in main memory.

In general, the present invention can be utilized in computer systems where the number of tag accesses per bus clock cycle is equal to bus II (number of bits) divided by accesses from the processor III (number of bits). would be obvious to the artist.

In the preferred embodiment, the processor is configurable for up to two tag accesses per bus clock cycle. The width of the bus is 64 bits, and the processor accesses 32 bits.

Each lot watcher monitors write transactions from its own processor to determine when cache writes occur and therefore when updates to its address tag occur. Whenever a microprocessor coupled to a cache memory attempts to perform a read operation that involves a main memory fetch (ie, there was no cache hit), the path watcher's address tag is updated. The bus watcher also monitors the device bus for write transactions from other processors. The address to be written is examined and a determination is made as to whether the address matches the address tag in this bus watcher. If there is a match, the corresponding bus watcher address tag array is invalidated and the entry in the cache is invalidated.

Bus watchers are designed to enforce consistency in computer systems such that a processor does not pay attention to the bus watcher when the processor attempts to perform a cache write.

This specification describes methods and apparatus for enforcing cache coherency. Numerous details such as bandwidth, processor class, etc. are set forth below in order to provide a thorough understanding of the invention.

However, it will be apparent to one skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits and techniques have not been described in detail in order not to unnecessarily obscure the present invention.

The present invention provides a method and apparatus for enforcing cache coherency in a computer system having multiple processors with separate write-mediated cache memories. Such devices may include any number of devices capable of accessing the system bus and updating memory (memory data). Each memory mu data can be combined with a cache memory as desired.

Cache memory is commonly used in computer systems as a high speed memory coupled directly to a central processing unit to buffer frequently accessed data and instruction read requests.

The processor unit of the preferred apparatus of the present invention is an integer processor unit (IPU) having an instruction and data cache.
and an interface to the device bus. In addition, the processor is a floating point processor unit (FPU)
It is also possible to have The instruction cache of the IPU is dedicated to start-up, and the data cache is a write intermediary cache that acts as a write buffer.

In the preferred embodiment computing system, there are two or more IPUs, each IPU having its own data cache. Further, the FPU associated with each IPU can modify the memory and does not refer to the cache memory. Therefore, a cache-inherent problem exists between the various data caches in the device. The preferred embodiment maintains cache volatility among data caches through aspects of bus supervision on the device bus. By bus monitoring
Which data in the cache can be matched to the data stored in main memory.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a device bus 1o and a processor device 11 that can be used in the present invention. In the preferred embodiment, device bus 10 has six
A 4-bit bus, the bus interface device 14
is coupled to processor 11 by. Bus interface device 14 is coupled to bus watcher 15 via address lines 24. Bus watcher 15 has an even address tag array 16 and an odd address tag array 17. Each entry in each tag array 16.17 represents an address associated with 32 bit data. Data within the device is transferred via a 64-bit bus. Therefore, data in the cache and corresponding entries in the address tag array can be updated in four bits (two words) per clock cycle. If a dual word bus transfer occurs, each odd and even address tag array 17.16 is examined for a match. If a single word or subword transfer occurs, only one of address tag arrays 16 and 17 is examined. Which address tag array to check depends on whether the address starts on an even word boundary or an odd word boundary.
It will be decided.

Bus watcher 15 is coupled to data cache memory 18 via line 26. In this example, the size of the data cache memory is 16 bytes. The cache memory 18 includes an even address tag array 19, an odd address tag array 20, an even data array 21,
It is composed of an odd number data array 22. The data cache is directly mapped (ie, entries in address tag array 19t or 20 have a one-to-one correspondence with entries in data array 21 or 22).

Data cache 18 is connected to processor 23 via line 2T.
is combined with This example is manufactured by MIPS Comput.rs, Sunnyvaj, California, USA.
uses a processor manufactured by processor 23
is coupled to bus interface device 14 via line 25. Line 25 is a bidirectional line that allows for one-way communication between processor 23 and bus interface 14 .

In addition to the processor 23, a floating point processor unit (
FPO) 3G can be coupled to the bus interface device 14. Device bus 1G can also be coupled to other devices 12, 13. The FPU 30 and devices fil 2 and 13 can update the main memory. However, in this embodiment they do not have separate cache memories.

These devices, whether cache memory or not, can be referred to as memory mu data.

FIG. 2 details a typical read operation. During a read operation, the processor may first attempt to read the cache by providing a physical address to the data cache memory (block 40). A data cache memory is provided to compare the nine physical addresses with the physical addresses in its even or odd address tag array.

The determination of which address tag array to compare is determined by whether the physical address starts on an even or odd word boundary. If a cache hit occurs, ie, the cache read is successful (block 41), a branch is taken (42) and the data is provided to the data cache array color microprocessor.

Assuming there is no data in the data cache memory, a memory fetch is performed by the microprocessor. The microprocessor of the MIPS computer used in this embodiment does not provide information as to whether the data determined by the memory 7 etch will be stored in the cache memory after a successful memory access. Therefore, whenever a memory fetch is performed by a processor, the path watcher updates its address tag with the address of the data to be fetched. Then,
Causes other entries in the bus watcher address tag array to be overwritten. If so, the corresponding data in the data cache array is invalidated (
block 45). Data may then be received from memory (block 46).

The processor then determines whether the cache should be updated. If the cache is to be updated, branch 48 is taken and the cache is updated (block 49).
). Otherwise, the cache is not updated (block 50). If the cache is updated (block 4
9), the data in the cache continues to match the address tag in the bus watcher. If the cache is not updated (branch 50), then the address tag in the bus watcher is the highest address tag in the cache. This method allows the bus watcher to determine whether data is present in the cache memory.

With brief reference to FIGS. 5 and 6, the method utilized in this embodiment for loading information from main memory to cache memory will now be described in detail.

In this embodiment, the device bus bandwidth is 2 words (64 bits, 32 bits = 1 word). Data is organized on a device bus 10, as shown in FIG.

In a given clock cycle, two words are communicated over the device bus 10, and a higher order O word 82 can be conveyed during the clock cycle 10. This alternative offers several inventive advantages. For example, in some computing devices, information from main memory is
It is advantageous to request in blocks of words rather than one word at a time. It is desirable to supply information to a cache memory associated with such a microprocessor in blocks of words.

As explained with reference to FIG.
A Microprocessor+J23 computer is used. This microprocessor has data cache memory 1
It has 8. The microprocessor can make requests for data, and cache misses 90 may occur that require access to main memory. It is aligned on the double word boundary lol! (i.e., an even addressed word) (branch 91), a double word read instruction is initiated on the device bus (block 9
2). A double word can match a high word 82 and a low word 81.

The device then selects the odd data cache array 22 as the cache to write to (block 94), and during clock cycle 0, the low order word 81 is received and written to the cache memory (block 95). Poulosetub originally sought words that were aligned on double word boundaries, that is, high-level words 82. The processor manager is instructed to correctly receive the compromised data and to retry the memory access (block 96).

The even data cache array 21 is then selected and receives the high order word 82 during clock cycle one. Next, that high rank ￥F! 82 is written to cache memory (block 98). The block then makes available the requested information, the high-level term 82. It will be apparent to those skilled in the art that in other embodiments of the invention, the specific order of the returned words may be varied. Specifically, in the computer system of this embodiment, the byte order is such that pi)0 is the leftmost byte. This can be described as a big-endian system (big-・ndl).
an 5yst@m), which conforms to the Motorola 68000 processor convention. The method and apparatus of the present invention provides that the byte order is
A similar application can be made to computer systems, such that byte O is the rightmost byte. This is called a little-endian system (title...ndiansystem).
m). In a little-endian system, the order can be reversed to that described in this example.

Because combinator devices often require sequential access to information, cache hits occur when requests are made for low-level words 81.

In this example, main memory access requires 10 clock cycles. Using the method of the invention, 11 clock cycles are required for rounding the double word access. Requires additional clock cycles for retry.

However, assuming the processor seeks to access low-level word 81, nine clock cycles are saved.

Additionally, the present invention utilizes 32 bits (one word) of bus bandwidth on a board within the device, such as processor board 11, and utilizes a device bus with a multiple word bandwidth. Therefore, jams can occur within the device as information is moved from the device bus to the board. The above-described retry method of the present invention allows sequential words in a booter block to be sent to boards within the device in a staggered manner. This solves the problem of jamming when the data word width is narrowed without degrading the performance of the device bus.

It will be apparent to those skilled in the art that the present invention can be utilized with computer devices having device bus bandwidths other than two words.

For example, a computer device can utilize 128 bits (4M) of device bus bandwidth. In that device, 1
~4 data cache memory arrays are available and data can be requested in blocks of 4 words. Data can be staggered in time over four clock cycles in the cache memory at a rate of one word per clock cycle.

Alternatively, block data can be received from the bus and placed in a buffer. Data is then received from the buffer into cache memory.

FIG. 3 illustrates how a bus watcher processes write transactions from its processor as may be utilized with the present invention. Since the path from the path watcher to the cache is a one-way path, the bus watcher is not alerted to writes to the cache. Instead, when the processor sends the write transaction to the write buffer (block TO), the write buffer indicates that the cache write has occurred (block 75).
and is responsible for storing information describing the write transaction and sending it to the bus interface (block 71).

Parallel K (block 71) with sending a write transaction to the bus interface, and if the new data is a write transaction to the cache, the cache can be updated with the new data (block 72).

The write buffer in this embodiment has a small matrix to avoid stalling the processor at critical times when the device bus is available. The bus interface then informs the bus watcher that the cache write has occurred (block 73) and places the transaction on the device bus when the device bus and memory are available. The bus watcher is then responsible for updating its address tag array and the address is written to memory (
block 74).

FIG. 4 shows how to override one cache entry when another processor, FPU, Ilo device, or graphics device writes information to main memory. In this embodiment, the processor employs a write-mediated cache mechanism configured such that data is written to main memory in direct correlation with data written to cache memory. In other words, the data is not kept in cache memory as dirty data until a future point in time when the cache memory is flushed to main memory; rather, once a write transaction to the cache occurs, the data is flushed to main memory as soon as possible. written to. In this embodiment, the computing device has several processor devices with separate caches. Each cache must be compatible with each other. Therefore, when a write transaction is performed with memory data, the corresponding cache entry must be invalidated.

In this embodiment, the bus watcher monitors the device path for write transactions and determines the address to write to (block 61). It does this by comparing it to the even or odd address tag array depending on whether the address begins on an even or odd word boundary.

Also, a transaction can be a double word transaction, and the path watcher must examine the even and odd tag arrays. If an address is not found in the watcher's address tag array (because the watcher's address tag array contains a superset of the data contained in the data cache for the processor), then the address is is not in the data cache for the write transaction, in which case branch 62 can be taken to ignore this write transaction.

Otherwise, branch 63 is taken and the corresponding entry in the Nox Watcher is invalidated (block 64).

Entries in the data cache memory are also invalidated (block 65). The next time the processor requests to read this data, there is no cache hit and the data must be fetched from memory as described with reference to FIG.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a computer device that can be used in the present invention and includes a number of central processing units having a cache memory and a bus watcher coupled to a central processing node; FIG. Regardless of whether there is a processor device that can be utilized in the present invention,
FIG. 3 is a flowchart illustrating a method for reading data and updating cache memory; FIG. FIG. 4 is a flow diagram of a method available to the present invention for monitoring write transactions from one external processor to ensure cache coherency; FIG. FIG. 6 is a flow diagram illustrating the method of the present invention for providing blocks of data to a cache memory when requested by a processor; FIG. 10...Device Hass, 11...Fist - Flosser device,
14...Pass interface device, 150 fists...
Bus watcher 16, 19... Even address tag array, 1γ, 20... Bone/odd address tag array, 18... Data cache memory, 21...
Even number data array, 22-...odd number data array, 2
3...Fist processor, 30...Floating rate JLa 7
'a Saying device.

Claims (5)

[Claims] (1) maintaining a list of identifying information for all entries in a first cache memory associated with a first processor; and monitoring write transactions to main memory by other processors in the computer device. and, when the write transaction addresses a location in the main memory that corresponds to an address in the list of identification information, invalidating a corresponding entry in the first cache memory, thereby . A method for enforcing cache coherency in a computing device, wherein a cache entry is invalidated in the first cache memory when the cache entry is inconsistent with an entry in the main memory. (2) having a plurality of processor units sharing one main memory, each said processor unit having a separate cache memory, said processors coupled to said main memory by a common bus, and each said memory connected to said processor unit; A method for enforcing cache coherency in a computing device, further comprising circuitry for monitoring transactions on the bus between a processor and a main memory, the circuitry monitoring transactions in the computing device, and comprising: in the case of a read transaction from the main memory by a first one of the cache memories, updating a tag in the circuit corresponding to an entry in a first cache memory associated with the first processor; in the case of a write transaction to the main memory by a first of the processors, determining from the tag whether information to be written is present in the first cache memory; The information to be entered is the first
invalidating the information if it exists in a cache memory of the first processor; and updating the tag based on the write transaction in the case of a write transaction from the first processor. , whereby a cache entry is invalidated in the first cache memory when the cache entry is inconsistent with an entry in the memory. (3) processor means for processing instructions; first means coupled to said processor means for storing information; first means coupled to said processor means for storing information;
second means having an access time shorter than the access time of said first means; and third means coupled to said processor and said first means for monitoring information sent to said first means. means; and a fourth means coupled to said third means and said second means for storing identification information about the contents of said second means.
A computer device comprising: means, whereby the contents of the second means are maintained consistent with the first means. (4) In a computer system having a number of processing units, one main memory shared by the processing units, and a plurality of separate high speed memories coupled to each said processing unit, each said processing unit and said processing unit said a plurality of first means coupled to main memory for monitoring transactions between each said processing unit and said main memory; and a plurality of first means coupled to each said high speed memory and said first means for determining addresses of data in said separate a plurality of second means for storing in high-speed memories; and a computer apparatus capable of maintaining a list of data in the separate high-speed memories consistent with the main memory. (5) an integer processing unit, a cache memory coupled to the integer processing unit, a device bus coupled to the cache memory, and a main memory coupled to the device path;
A computing device comprising the integer processing device and a floating point processing device coupled to the device path, comprising: maintaining a list of identification information for all entries in the cache memory; monitoring a write transaction to main memory; and if said write transaction addresses a location in said main memory corresponding to an address in said list of identification information, said write transaction addresses a location in said first cache memory that corresponds to an address in said list of identification information; 1. A method of enforcing cache coherence in a computing device, comprising: a process of invalidating entries;