IT1225680B - Equipment for rapid recognition of packets of data in digital telecommunications systems without prior linking of the clock to the word of alignment - Google Patents

Equipment for rapid recognition of packets of data in digital telecommunications systems without prior linking of the clock to the word of alignment

Info

Publication number
IT1225680B
IT1225680B IT8812534A IT1253488A IT1225680B IT 1225680 B IT1225680 B IT 1225680B IT 8812534 A IT8812534 A IT 8812534A IT 1253488 A IT1253488 A IT 1253488A IT 1225680 B IT1225680 B IT 1225680B
Authority
IT
Italy
Prior art keywords
alignment
packets
data
word
clock
Prior art date
Application number
IT8812534A
Other languages
Italian (it)
Other versions
IT8812534A0 (en
Inventor
Bruno Biancardi
Original Assignee
Marconi Italiana
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Italiana filed Critical Marconi Italiana
Priority to IT8812534A priority Critical patent/IT1225680B/en
Publication of IT8812534A0 publication Critical patent/IT8812534A0/en
Application granted granted Critical
Publication of IT1225680B publication Critical patent/IT1225680B/en

Links

Abstract

In order to recognise rapidly packets of data in digital telecommunications systems, without having to link the clock in advance to the word of alignment, preferably at least three or more search clocks are generated, which are unrelated to the incoming signal, isofrequential to each other and out of phase by an amplitude at 1/n of 360 degrees, where "n" equals the number of clocks in question. The search clocks control the respective shift registers (SR1-SR2-SR3), which receive the incoming packets of data with the alignment word and the output from the registers goes into a memory (17), which recognises the alignment word and which gives an output enable signal (Ic), only when at an entry point it receives, from one of the said registers, the signal corresponding to reading and storage upon the alignment word stage having taken place. The output form the memory goes to a selector (18) which receives the input of the search clocks and which allows only that clock to exit which has carried out the reading each time at the alignment word stage. The selector's exit, together with the signal with the packets of data received, finally goes to a known reading unit (19) for the information data.
IT8812534A 1988-08-03 1988-08-03 Equipment for rapid recognition of packets of data in digital telecommunications systems without prior linking of the clock to the word of alignment IT1225680B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
IT8812534A IT1225680B (en) 1988-08-03 1988-08-03 Equipment for rapid recognition of packets of data in digital telecommunications systems without prior linking of the clock to the word of alignment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8812534A IT1225680B (en) 1988-08-03 1988-08-03 Equipment for rapid recognition of packets of data in digital telecommunications systems without prior linking of the clock to the word of alignment

Publications (2)

Publication Number Publication Date
IT8812534A0 IT8812534A0 (en) 1988-08-03
IT1225680B true IT1225680B (en) 1990-11-22

Family

ID=11141289

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8812534A IT1225680B (en) 1988-08-03 1988-08-03 Equipment for rapid recognition of packets of data in digital telecommunications systems without prior linking of the clock to the word of alignment

Country Status (1)

Country Link
IT (1) IT1225680B (en)

Also Published As

Publication number Publication date
IT8812534A0 (en) 1988-08-03

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970828