IT1220189B - Metodo per aumentare incrementalmente in fase di collaudo elettrico su fetta di un dispositivo integrato l'area di collettore di un transistore pnp laterale - Google Patents
Metodo per aumentare incrementalmente in fase di collaudo elettrico su fetta di un dispositivo integrato l'area di collettore di un transistore pnp lateraleInfo
- Publication number
- IT1220189B IT1220189B IT83683/87A IT8368387A IT1220189B IT 1220189 B IT1220189 B IT 1220189B IT 83683/87 A IT83683/87 A IT 83683/87A IT 8368387 A IT8368387 A IT 8368387A IT 1220189 B IT1220189 B IT 1220189B
- Authority
- IT
- Italy
- Prior art keywords
- slice
- phase
- integrated device
- pnp transistor
- collector area
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/30—Marginal testing, e.g. by varying supply voltage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT83683/87A IT1220189B (it) | 1987-12-22 | 1987-12-22 | Metodo per aumentare incrementalmente in fase di collaudo elettrico su fetta di un dispositivo integrato l'area di collettore di un transistore pnp laterale |
DE88830552T DE3885257T2 (de) | 1987-12-22 | 1988-12-21 | Verfahren, um die Kollektorfläche eines lateralen PNP Transistors differentiel zu vergrössern während des elektrischen Tests einer integrierten Schaltung auf einem Wafer. |
EP88830552A EP0322380B1 (en) | 1987-12-22 | 1988-12-21 | A method for incrementally increasing the collector area of a lateral PNP transistor during electrical testing of an integrated device on wafer |
US07/288,163 US4910159A (en) | 1987-12-22 | 1988-12-22 | Method for incrementally increasing the collector area of a lateral PNP transistor during electrical testing of an integrated device on wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT83683/87A IT1220189B (it) | 1987-12-22 | 1987-12-22 | Metodo per aumentare incrementalmente in fase di collaudo elettrico su fetta di un dispositivo integrato l'area di collettore di un transistore pnp laterale |
Publications (2)
Publication Number | Publication Date |
---|---|
IT8783683A0 IT8783683A0 (it) | 1987-12-22 |
IT1220189B true IT1220189B (it) | 1990-06-06 |
Family
ID=11323798
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT83683/87A IT1220189B (it) | 1987-12-22 | 1987-12-22 | Metodo per aumentare incrementalmente in fase di collaudo elettrico su fetta di un dispositivo integrato l'area di collettore di un transistore pnp laterale |
Country Status (4)
Country | Link |
---|---|
US (1) | US4910159A (it) |
EP (1) | EP0322380B1 (it) |
DE (1) | DE3885257T2 (it) |
IT (1) | IT1220189B (it) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4042740B4 (de) * | 1989-07-20 | 2004-09-09 | Hitachi, Ltd. | Sensor |
DE4042719C2 (de) * | 1989-07-20 | 2003-01-30 | Hitachi Ltd | Sensor |
JP3145694B2 (ja) * | 1990-08-28 | 2001-03-12 | 日本電気株式会社 | 半導体装置 |
US5610079A (en) * | 1995-06-19 | 1997-03-11 | Reliance Electric Industrial Company | Self-biased moat for parasitic current suppression in integrated circuits |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3761787A (en) * | 1971-09-01 | 1973-09-25 | Motorola Inc | Method and apparatus for adjusting transistor current |
US3958267A (en) * | 1973-05-07 | 1976-05-18 | National Semiconductor Corporation | Current scaling in lateral pnp structures |
JPS5216943A (en) * | 1975-07-30 | 1977-02-08 | Hitachi Ltd | Analog operation circuit |
US4451839A (en) * | 1980-09-12 | 1984-05-29 | National Semiconductor Corporation | Bilateral zener trim |
US4646427A (en) * | 1984-06-28 | 1987-03-03 | Motorola, Inc. | Method of electrically adjusting the zener knee of a lateral polysilicon zener diode |
US4775884A (en) * | 1984-08-03 | 1988-10-04 | Linear Technology Corporation | Integrated circuit having permanent adjustment circuitry which requires low adjustment current |
DE3526485A1 (de) * | 1985-07-24 | 1987-02-05 | Heinz Krug | Schaltungsanordnung zum pruefen integrierter schaltungseinheiten |
FR2592526B1 (fr) * | 1985-12-31 | 1988-10-14 | Radiotechnique Compelec | Circuit integre comportant un transistor lateral |
US4730127A (en) * | 1986-12-22 | 1988-03-08 | Motorola, Inc. | Method of matching currents from split collector lateral pnp transistors |
US4820657A (en) * | 1987-02-06 | 1989-04-11 | Georgia Tech Research Corporation | Method for altering characteristics of junction semiconductor devices |
-
1987
- 1987-12-22 IT IT83683/87A patent/IT1220189B/it active
-
1988
- 1988-12-21 DE DE88830552T patent/DE3885257T2/de not_active Expired - Fee Related
- 1988-12-21 EP EP88830552A patent/EP0322380B1/en not_active Expired - Lifetime
- 1988-12-22 US US07/288,163 patent/US4910159A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0322380B1 (en) | 1993-10-27 |
IT8783683A0 (it) | 1987-12-22 |
US4910159A (en) | 1990-03-20 |
DE3885257D1 (de) | 1993-12-02 |
DE3885257T2 (de) | 1994-02-17 |
EP0322380A3 (en) | 1991-03-13 |
EP0322380A2 (en) | 1989-06-28 |
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Legal Events
Date | Code | Title | Description |
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TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19961227 |