IT1215023B - Dispositivo e semiconduttore incapsulato in resina ed elettronicamente isolato e procedimento per lasua fabbricazione - Google Patents

Dispositivo e semiconduttore incapsulato in resina ed elettronicamente isolato e procedimento per lasua fabbricazione

Info

Publication number
IT1215023B
IT1215023B IT8606611A IT661186A IT1215023B IT 1215023 B IT1215023 B IT 1215023B IT 8606611 A IT8606611 A IT 8606611A IT 661186 A IT661186 A IT 661186A IT 1215023 B IT1215023 B IT 1215023B
Authority
IT
Italy
Prior art keywords
lasua
semiconductor
manufacture
resin
encapsulated device
Prior art date
Application number
IT8606611A
Other languages
English (en)
Italian (it)
Other versions
IT8606611A0 (it
Inventor
Spatriciano Permicioro Antonio
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT8606611A priority Critical patent/IT1215023B/it
Publication of IT8606611A0 publication Critical patent/IT8606611A0/it
Priority to EP87201454A priority patent/EP0257681A3/en
Priority to PH35722A priority patent/PH25368A/en
Priority to JP62209401A priority patent/JPS6362239A/ja
Priority to KR1019870009326A priority patent/KR880003426A/ko
Priority to US07/090,142 priority patent/US4888307A/en
Priority to MYPI87001498A priority patent/MY102351A/en
Application granted granted Critical
Publication of IT1215023B publication Critical patent/IT1215023B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
IT8606611A 1986-08-27 1986-08-27 Dispositivo e semiconduttore incapsulato in resina ed elettronicamente isolato e procedimento per lasua fabbricazione IT1215023B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT8606611A IT1215023B (it) 1986-08-27 1986-08-27 Dispositivo e semiconduttore incapsulato in resina ed elettronicamente isolato e procedimento per lasua fabbricazione
EP87201454A EP0257681A3 (en) 1986-08-27 1987-07-30 Method for manufacturing plastic encapsulated semiconductor devices and devices obtained thereby
PH35722A PH25368A (en) 1986-08-27 1987-08-24 Method for manufacturing plastic encapsulated semiconducter devices
JP62209401A JPS6362239A (ja) 1986-08-27 1987-08-25 プラスチックカプセル封じ半導体デバイスの製造方法
KR1019870009326A KR880003426A (ko) 1986-08-27 1987-08-26 플라스틱 캡슐형 반도체 장치 및 이의 제조 방법
US07/090,142 US4888307A (en) 1986-08-27 1987-08-27 Method for manufacturing plastic encapsulated semiconductor devices
MYPI87001498A MY102351A (en) 1986-08-27 1987-09-01 Encapsulation for semiconductor devices.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8606611A IT1215023B (it) 1986-08-27 1986-08-27 Dispositivo e semiconduttore incapsulato in resina ed elettronicamente isolato e procedimento per lasua fabbricazione

Publications (2)

Publication Number Publication Date
IT8606611A0 IT8606611A0 (it) 1986-08-27
IT1215023B true IT1215023B (it) 1990-01-31

Family

ID=11121391

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8606611A IT1215023B (it) 1986-08-27 1986-08-27 Dispositivo e semiconduttore incapsulato in resina ed elettronicamente isolato e procedimento per lasua fabbricazione

Country Status (3)

Country Link
JP (1) JPS6362239A (ko)
KR (1) KR880003426A (ko)
IT (1) IT1215023B (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2596995B2 (ja) * 1988-12-21 1997-04-02 シャープ株式会社 半導体装置の製造方法
JP2752677B2 (ja) * 1989-01-11 1998-05-18 日本電気株式会社 半導体装置の製造方法
JPH02216838A (ja) * 1989-02-17 1990-08-29 Fuji Electric Co Ltd 樹脂封止型半導体装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130129A (ja) * 1983-12-16 1985-07-11 Nec Corp 絶縁型半導体素子の樹脂封止方法

Also Published As

Publication number Publication date
IT8606611A0 (it) 1986-08-27
KR880003426A (ko) 1988-05-17
JPS6362239A (ja) 1988-03-18

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970829