IT1212404B - METHOD OF A SINGLE ATTACK FOR THE FORMATION OF A MESA PRESENTING A MULTIPLE WALL. - Google Patents

METHOD OF A SINGLE ATTACK FOR THE FORMATION OF A MESA PRESENTING A MULTIPLE WALL.

Info

Publication number
IT1212404B
IT1212404B IT8019547A IT1954780A IT1212404B IT 1212404 B IT1212404 B IT 1212404B IT 8019547 A IT8019547 A IT 8019547A IT 1954780 A IT1954780 A IT 1954780A IT 1212404 B IT1212404 B IT 1212404B
Authority
IT
Italy
Prior art keywords
mesa
presenting
formation
multiple wall
single attack
Prior art date
Application number
IT8019547A
Other languages
Italian (it)
Other versions
IT8019547A0 (en
Inventor
Einthoven Willelm Gerard
Manning Savidge Neilson John
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Publication of IT8019547A0 publication Critical patent/IT8019547A0/en
Application granted granted Critical
Publication of IT1212404B publication Critical patent/IT1212404B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Bipolar Transistors (AREA)
  • Weting (AREA)
IT8019547A 1979-02-22 1980-01-29 METHOD OF A SINGLE ATTACK FOR THE FORMATION OF A MESA PRESENTING A MULTIPLE WALL. IT1212404B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US1414479A 1979-02-22 1979-02-22

Publications (2)

Publication Number Publication Date
IT8019547A0 IT8019547A0 (en) 1980-01-29
IT1212404B true IT1212404B (en) 1989-11-22

Family

ID=21763796

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8019547A IT1212404B (en) 1979-02-22 1980-01-29 METHOD OF A SINGLE ATTACK FOR THE FORMATION OF A MESA PRESENTING A MULTIPLE WALL.

Country Status (5)

Country Link
JP (1) JPS55115335A (en)
DE (1) DE3005627A1 (en)
FR (1) FR2449971A1 (en)
GB (1) GB2042805A (en)
IT (1) IT1212404B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8624637D0 (en) * 1986-10-14 1986-11-19 Emi Plc Thorn Electrical device
US4996627A (en) * 1989-01-30 1991-02-26 Dresser Industries, Inc. High sensitivity miniature pressure transducer
EP2717314A1 (en) * 2012-10-03 2014-04-09 ABB Technology AG Method of producing a junction termination for a power semiconductor device and corresponding power semiconductor device
FR2998090A1 (en) * 2013-06-26 2014-05-16 Commissariat Energie Atomique Method for structuring material surface of substrate for producing e.g. nanometric patterns on surface for LEDs, involves forming patterns due to difference between etch selectivity of material and changed etch selectivity of regions
FR3030876B1 (en) 2014-12-22 2017-12-15 Commissariat Energie Atomique METHOD OF MAKING REASONS

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL153947B (en) * 1967-02-25 1977-07-15 Philips Nv PROCEDURE FOR MANUFACTURING SEMICONDUCTOR DEVICES, USING A SELECTIVE ELECTROLYTIC ETCHING PROCESS AND OBTAINING SEMI-CONDUCTOR DEVICE BY APPLICATION OF THE PROCESS.
NL162254B (en) * 1968-11-29 1979-11-15 Philips Nv SEMI-CONDUCTOR DEVICE FOR CONVERSION OF MECHANICAL VOLTAGES INTO ELECTRICAL SIGNALS AND METHOD OF MANUFACTURING THIS.
GB1211499A (en) * 1969-03-07 1970-11-04 Standard Telephones Cables Ltd A method of manufacturing semiconductor devices
NL180265C (en) * 1976-06-21 1987-01-16 Gen Electric SEMICONDUCTOR FOR HIGH VOLTAGE.
JPS5360580A (en) * 1976-11-11 1978-05-31 Nec Corp Etching method of semiconductor material
JPS53120280A (en) * 1977-03-30 1978-10-20 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
DE3005627A1 (en) 1980-09-04
FR2449971A1 (en) 1980-09-19
IT8019547A0 (en) 1980-01-29
GB2042805A (en) 1980-09-24
JPS55115335A (en) 1980-09-05

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