IT1161684B - Cmos ad alta tensione con ossidazione localizzata per anelli di guardia autoallineati e relativo processo di fabbricazione - Google Patents

Cmos ad alta tensione con ossidazione localizzata per anelli di guardia autoallineati e relativo processo di fabbricazione

Info

Publication number
IT1161684B
IT1161684B IT12700/78A IT1270078A IT1161684B IT 1161684 B IT1161684 B IT 1161684B IT 12700/78 A IT12700/78 A IT 12700/78A IT 1270078 A IT1270078 A IT 1270078A IT 1161684 B IT1161684 B IT 1161684B
Authority
IT
Italy
Prior art keywords
self
high voltage
manufacturing process
guard rings
voltage cmos
Prior art date
Application number
IT12700/78A
Other languages
English (en)
Italian (it)
Other versions
IT7812700A0 (it
Original Assignee
Harris Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harris Corp filed Critical Harris Corp
Publication of IT7812700A0 publication Critical patent/IT7812700A0/it
Application granted granted Critical
Publication of IT1161684B publication Critical patent/IT1161684B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H10W10/0127—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers using both n-type and p-type impurities, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/07—Guard rings and cmos
IT12700/78A 1977-09-21 1978-07-07 Cmos ad alta tensione con ossidazione localizzata per anelli di guardia autoallineati e relativo processo di fabbricazione IT1161684B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/835,263 US4135955A (en) 1977-09-21 1977-09-21 Process for fabricating high voltage cmos with self-aligned guard rings utilizing selective diffusion and local oxidation

Publications (2)

Publication Number Publication Date
IT7812700A0 IT7812700A0 (it) 1978-07-07
IT1161684B true IT1161684B (it) 1987-03-18

Family

ID=25269065

Family Applications (1)

Application Number Title Priority Date Filing Date
IT12700/78A IT1161684B (it) 1977-09-21 1978-07-07 Cmos ad alta tensione con ossidazione localizzata per anelli di guardia autoallineati e relativo processo di fabbricazione

Country Status (5)

Country Link
US (1) US4135955A (OSRAM)
DE (1) DE2816795A1 (OSRAM)
FR (1) FR2404300A1 (OSRAM)
GB (1) GB1581498A (OSRAM)
IT (1) IT1161684B (OSRAM)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485390A (en) * 1978-03-27 1984-11-27 Ncr Corporation Narrow channel FET
US4313768A (en) * 1978-04-06 1982-02-02 Harris Corporation Method of fabricating improved radiation hardened self-aligned CMOS having Si doped Al field gate
US4402002A (en) * 1978-04-06 1983-08-30 Harris Corporation Radiation hardened-self aligned CMOS and method of fabrication
IT1166587B (it) * 1979-01-22 1987-05-05 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari ad alta integrazione per tensioni elevate
US4295897B1 (en) * 1979-10-03 1997-09-09 Texas Instruments Inc Method of making cmos integrated circuit device
US4295266A (en) * 1980-06-30 1981-10-20 Rca Corporation Method of manufacturing bulk CMOS integrated circuits
GB2084794B (en) * 1980-10-03 1984-07-25 Philips Electronic Associated Methods of manufacturing insulated gate field effect transistors
JPS5791553A (en) * 1980-11-29 1982-06-07 Toshiba Corp Semiconductor device
US4385947A (en) * 1981-07-29 1983-05-31 Harris Corporation Method for fabricating CMOS in P substrate with single guard ring using local oxidation
US4613885A (en) * 1982-02-01 1986-09-23 Texas Instruments Incorporated High-voltage CMOS process
US4435895A (en) 1982-04-05 1984-03-13 Bell Telephone Laboratories, Incorporated Process for forming complementary integrated circuit devices
IT1210872B (it) * 1982-04-08 1989-09-29 Ates Componenti Elettron Processo per la fabbricazione di transistori mos complementari in circuiti integrati ad alta densita' per tensioni elevate.
US4412375A (en) * 1982-06-10 1983-11-01 Intel Corporation Method for fabricating CMOS devices with guardband
US4480375A (en) * 1982-12-09 1984-11-06 International Business Machines Corporation Simple process for making complementary transistors
US4471523A (en) * 1983-05-02 1984-09-18 International Business Machines Corporation Self-aligned field implant for oxide-isolated CMOS FET
US4574467A (en) * 1983-08-31 1986-03-11 Solid State Scientific, Inc. N- well CMOS process on a P substrate with double field guard rings and a PMOS buried channel
US4517731A (en) * 1983-09-29 1985-05-21 Fairchild Camera & Instrument Corporation Double polysilicon process for fabricating CMOS integrated circuits
US4567640A (en) * 1984-05-22 1986-02-04 Data General Corporation Method of fabricating high density CMOS devices
US4600445A (en) * 1984-09-14 1986-07-15 International Business Machines Corporation Process for making self aligned field isolation regions in a semiconductor substrate
US4757363A (en) * 1984-09-14 1988-07-12 Harris Corporation ESD protection network for IGFET circuits with SCR prevention guard rings
US4713329A (en) * 1985-07-22 1987-12-15 Data General Corporation Well mask for CMOS process
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
TW328650B (en) * 1996-08-27 1998-03-21 United Microelectronics Corp The MOS device and its manufacturing method
JP3931138B2 (ja) * 2002-12-25 2007-06-13 三菱電機株式会社 電力用半導体装置及び電力用半導体装置の製造方法
RU2674415C1 (ru) * 2018-03-06 2018-12-07 Акционерное общество Научно-производственный центр "Электронные вычислительно-информационные системы" (АО НПЦ "ЭЛВИС") Радиационно-стойкая библиотека элементов на комплементарных металл-окисел-полупроводник транзисторах

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673428A (en) * 1970-09-18 1972-06-27 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
US3712995A (en) * 1972-03-27 1973-01-23 Rca Corp Input transient protection for complementary insulated gate field effect transistor integrated circuit device
US3853633A (en) * 1972-12-04 1974-12-10 Motorola Inc Method of making a semi planar insulated gate field-effect transistor device with implanted field
US3888706A (en) * 1973-08-06 1975-06-10 Rca Corp Method of making a compact guard-banded mos integrated circuit device using framelike diffusion-masking structure
US4027380A (en) * 1974-06-03 1977-06-07 Fairchild Camera And Instrument Corporation Complementary insulated gate field effect transistor structure and process for fabricating the structure
US3983620A (en) * 1975-05-08 1976-10-05 National Semiconductor Corporation Self-aligned CMOS process for bulk silicon and insulating substrate device
US4006491A (en) * 1975-05-15 1977-02-01 Motorola, Inc. Integrated circuit having internal main supply voltage regulator
US4045250A (en) * 1975-08-04 1977-08-30 Rca Corporation Method of making a semiconductor device
JPS5286083A (en) * 1976-01-12 1977-07-16 Hitachi Ltd Production of complimentary isolation gate field effect transistor
US4013484A (en) * 1976-02-25 1977-03-22 Intel Corporation High density CMOS process

Also Published As

Publication number Publication date
DE2816795A1 (de) 1979-04-05
US4135955A (en) 1979-01-23
FR2404300A1 (fr) 1979-04-20
DE2816795C2 (OSRAM) 1989-10-05
IT7812700A0 (it) 1978-07-07
GB1581498A (en) 1980-12-17
FR2404300B1 (OSRAM) 1983-01-21

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960729