IT1115341B - Apparecchiatura perfezionata per controllare circuiti orologio in sistemi di calcolo - Google Patents

Apparecchiatura perfezionata per controllare circuiti orologio in sistemi di calcolo

Info

Publication number
IT1115341B
IT1115341B IT24416/77A IT2441677A IT1115341B IT 1115341 B IT1115341 B IT 1115341B IT 24416/77 A IT24416/77 A IT 24416/77A IT 2441677 A IT2441677 A IT 2441677A IT 1115341 B IT1115341 B IT 1115341B
Authority
IT
Italy
Prior art keywords
control clock
clock circuits
improved equipment
calculation systems
calculation
Prior art date
Application number
IT24416/77A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1115341B publication Critical patent/IT1115341B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
IT24416/77A 1976-06-30 1977-06-07 Apparecchiatura perfezionata per controllare circuiti orologio in sistemi di calcolo IT1115341B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/701,053 US4071902A (en) 1976-06-30 1976-06-30 Reduced overhead for clock testing in a level system scan design (LSSD) system

Publications (1)

Publication Number Publication Date
IT1115341B true IT1115341B (it) 1986-02-03

Family

ID=24815880

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24416/77A IT1115341B (it) 1976-06-30 1977-06-07 Apparecchiatura perfezionata per controllare circuiti orologio in sistemi di calcolo

Country Status (6)

Country Link
US (1) US4071902A (it)
JP (1) JPS533752A (it)
DE (1) DE2720863A1 (it)
FR (1) FR2357005A1 (it)
GB (1) GB1581864A (it)
IT (1) IT1115341B (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4244048A (en) * 1978-12-29 1981-01-06 International Business Machines Corporation Chip and wafer configuration and testing method for large-scale-integrated circuits
US4264807A (en) * 1979-04-09 1981-04-28 International Business Machines Corporation Counter including two 2 bit counter segments connected in cascade each counting in Gray code
DE3029883A1 (de) * 1980-08-07 1982-03-11 Ibm Deutschland Gmbh, 7000 Stuttgart Schieberegister fuer pruef- und test-zwecke
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4488259A (en) * 1982-10-29 1984-12-11 Ibm Corporation On chip monitor
US4503537A (en) * 1982-11-08 1985-03-05 International Business Machines Corporation Parallel path self-testing system
JPS59119917A (ja) * 1982-12-27 1984-07-11 Toshiba Corp 論理回路
US4554664A (en) * 1983-10-06 1985-11-19 Sperry Corporation Static memory cell with dynamic scan test latch
US4580066A (en) * 1984-03-22 1986-04-01 Sperry Corporation Fast scan/set testable latch using two levels of series gating with two current sources
JPS6188538A (ja) * 1984-10-05 1986-05-06 Fujitsu Ltd 半導体装置
GB2171231B (en) * 1985-02-14 1989-11-01 Intel Corp Software programmable logic array
JPH0296963A (ja) * 1988-10-03 1990-04-09 Hitachi Ltd 半導体集積回路装置
US4972414A (en) * 1989-11-13 1990-11-20 International Business Machines Corporation Method and apparatus for detecting oscillator stuck faults in a level sensitive scan design (LSSD) system
US5684808A (en) * 1995-09-19 1997-11-04 Unisys Corporation System and method for satisfying mutually exclusive gating requirements in automatic test pattern generation systems
US5640402A (en) * 1995-12-08 1997-06-17 International Business Machines Corporation Fast flush load of LSSD SRL chains
US6327685B1 (en) 1999-05-12 2001-12-04 International Business Machines Corporation Logic built-in self test
US6442720B1 (en) 1999-06-04 2002-08-27 International Business Machines Corporation Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis
US7350124B2 (en) * 2005-10-18 2008-03-25 International Business Machines Corporation Method and apparatus for accelerating through-the pins LBIST simulation
US7908532B2 (en) * 2008-02-16 2011-03-15 International Business Machines Corporation Automated system and processing for expedient diagnosis of broken shift registers latch chains
US9108766B2 (en) 2013-07-19 2015-08-18 S.C. Johnson & Son, Inc. Storage container systems

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851187A (en) * 1971-03-05 1974-11-26 H Pao High speed shift register with t-t-l compatibility
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US3784907A (en) * 1972-10-16 1974-01-08 Ibm Method of propagation delay testing a functional logic system
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
FR2330014A1 (fr) * 1973-05-11 1977-05-27 Ibm France Procede de test de bloc de circuits logiques integres et blocs en faisant application
US3983538A (en) * 1974-05-01 1976-09-28 International Business Machines Corporation Universal LSI array logic modules with integral storage array and variable autonomous sequencing

Also Published As

Publication number Publication date
DE2720863A1 (de) 1978-01-05
FR2357005A1 (fr) 1978-01-27
FR2357005B1 (it) 1979-03-09
JPS533752A (en) 1978-01-13
US4071902A (en) 1978-01-31
GB1581864A (en) 1980-12-31

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