IT1091633B - Dispositivo per la gestione del l accesso diretto alla memoria di un calcolatore - Google Patents

Dispositivo per la gestione del l accesso diretto alla memoria di un calcolatore

Info

Publication number
IT1091633B
IT1091633B IT69952/77A IT6995277A IT1091633B IT 1091633 B IT1091633 B IT 1091633B IT 69952/77 A IT69952/77 A IT 69952/77A IT 6995277 A IT6995277 A IT 6995277A IT 1091633 B IT1091633 B IT 1091633B
Authority
IT
Italy
Prior art keywords
management
memory
computer
direct access
access
Prior art date
Application number
IT69952/77A
Other languages
English (en)
Italian (it)
Original Assignee
Olivetti C Ing E C Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olivetti C Ing E C Spa filed Critical Olivetti C Ing E C Spa
Priority to IT69952/77A priority Critical patent/IT1091633B/it
Priority to US05/971,322 priority patent/US4245305A/en
Priority to DE19782855673 priority patent/DE2855673A1/de
Priority to GB7850136A priority patent/GB2011681B/en
Application granted granted Critical
Publication of IT1091633B publication Critical patent/IT1091633B/it

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18Handling requests for interconnection or transfer for access to memory bus based on priority control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287Multiplexed DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
IT69952/77A 1977-12-30 1977-12-30 Dispositivo per la gestione del l accesso diretto alla memoria di un calcolatore IT1091633B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT69952/77A IT1091633B (it) 1977-12-30 1977-12-30 Dispositivo per la gestione del l accesso diretto alla memoria di un calcolatore
US05/971,322 US4245305A (en) 1977-12-30 1978-12-20 Direct memory access control device
DE19782855673 DE2855673A1 (de) 1977-12-30 1978-12-21 Anordnung zur handhabung des direkten zugriffs auf den speicher einer datenverarbeitungsanlage
GB7850136A GB2011681B (en) 1977-12-30 1978-12-28 Arrangement for handling direct access to the momory of a computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT69952/77A IT1091633B (it) 1977-12-30 1977-12-30 Dispositivo per la gestione del l accesso diretto alla memoria di un calcolatore

Publications (1)

Publication Number Publication Date
IT1091633B true IT1091633B (it) 1985-07-06

Family

ID=11313161

Family Applications (1)

Application Number Title Priority Date Filing Date
IT69952/77A IT1091633B (it) 1977-12-30 1977-12-30 Dispositivo per la gestione del l accesso diretto alla memoria di un calcolatore

Country Status (4)

Country Link
US (1) US4245305A (cg-RX-API-DMAC10.html)
DE (1) DE2855673A1 (cg-RX-API-DMAC10.html)
GB (1) GB2011681B (cg-RX-API-DMAC10.html)
IT (1) IT1091633B (cg-RX-API-DMAC10.html)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4400772A (en) * 1980-12-30 1983-08-23 International Memories, Inc. Method and apparatus for direct memory access in a data processing system
DE3119812A1 (de) * 1981-05-19 1982-12-16 Kienzle Apparate Gmbh, 7730 Villingen-Schwenningen Elektronischer taxameter
WO1983001135A1 (en) * 1981-09-18 1983-03-31 Rovsing As Christian Multiprocessor computer system
DE3241402A1 (de) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum steuern des datentransfers zwischen einem datensender und einem datenempfaenger ueber einen bus mit hilfe einer am bus angeschlossenen steuereinrichtung
DE3241376A1 (de) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München Dma-steuereinrichtung zur uebertragung von daten zwischen einem datensender und einem datenempfaenger
DE3501569C2 (de) * 1984-01-20 1996-07-18 Canon Kk Datenverarbeitungseinrichtung
US4773000A (en) * 1984-01-23 1988-09-20 Raytheon Company DMA for digital computer system
CA1218161A (en) * 1984-01-23 1987-02-17 Stanley M. Nissen Direct memory access controller
US4688166A (en) * 1984-08-03 1987-08-18 Motorola Computer Systems, Inc. Direct memory access controller supporting multiple input/output controllers and memory units
DE3602851A1 (de) * 1986-01-31 1987-08-06 Wulfhard Dipl Phys Schneider Datenverarbeitungssystem mit kurzen antwortzeiten auf aeussere ereignisse
US5018098A (en) * 1987-05-07 1991-05-21 Fujitsu Limited Data transfer controlling apparatus for direct memory access
JPH01293431A (ja) * 1988-05-23 1989-11-27 Toshiba Corp メモリアクセス方式
US5276845A (en) * 1988-08-25 1994-01-04 Yamaha Corporation Apparatus with multiple buses for permitting concurrent access to a first memory by a processor while a DMA transfer is occurring between a second memory and a communications buffer
US4935868A (en) * 1988-11-28 1990-06-19 Ncr Corporation Multiple port bus interface controller with slave bus
FR2687487B1 (fr) * 1992-02-19 1996-12-20 Alcatel Business Systems Systeme de partage de temps d'acces a une memoire partagee entre un processeur et d'autres applications.
US5513374A (en) * 1993-09-27 1996-04-30 Hitachi America, Inc. On-chip interface and DMA controller with interrupt functions for digital signal processor
US5740404A (en) * 1993-09-27 1998-04-14 Hitachi America Limited Digital signal processor with on-chip select decoder and wait state generator
US5826106A (en) * 1995-05-26 1998-10-20 National Semiconductor Corporation High performance multifunction direct memory access (DMA) controller
JP2914261B2 (ja) * 1995-12-20 1999-06-28 富士ゼロックス株式会社 外部記憶制御装置及び外部記憶装置制御方法
GB2309559B (en) * 1996-01-27 2000-01-26 Motorola Israel Ltd Microprocessor and system
US5913075A (en) * 1997-03-25 1999-06-15 International Business Machines Corporation High speed communication between high cycle rate electronic devices using a low cycle rate bus
US6101561A (en) * 1998-02-06 2000-08-08 International Business Machines Corporation System for providing an increase in digital data transmission rate over a parallel bus by converting binary format voltages to encoded analog format currents
CN101006433B (zh) * 2004-08-25 2012-01-11 日本电气株式会社 信息通信装置和程序执行环境控制方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3133268A (en) * 1959-03-09 1964-05-12 Teleregister Corp Revisable data storage and rapid answer back system
US3526878A (en) * 1967-03-27 1970-09-01 Burroughs Corp Digital computer system
US3703707A (en) * 1971-04-28 1972-11-21 Burroughs Corp Dual clock memory access control
US4053950A (en) * 1976-04-30 1977-10-11 International Business Machines Corporation Residual status reporting during chained cycle steal input/output operations

Also Published As

Publication number Publication date
DE2855673C2 (cg-RX-API-DMAC10.html) 1990-04-19
US4245305A (en) 1981-01-13
GB2011681B (en) 1982-07-07
DE2855673A1 (de) 1979-07-05
GB2011681A (en) 1979-07-11

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227