IT1032558B - Sistema per generare un multiplon di una frequenza normale - Google Patents

Sistema per generare un multiplon di una frequenza normale

Info

Publication number
IT1032558B
IT1032558B IT70707/74A IT7070774A IT1032558B IT 1032558 B IT1032558 B IT 1032558B IT 70707/74 A IT70707/74 A IT 70707/74A IT 7070774 A IT7070774 A IT 7070774A IT 1032558 B IT1032558 B IT 1032558B
Authority
IT
Italy
Prior art keywords
multiplon
generate
normal frequency
frequency
normal
Prior art date
Application number
IT70707/74A
Other languages
English (en)
Italian (it)
Original Assignee
Hasler Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hasler Ag filed Critical Hasler Ag
Application granted granted Critical
Publication of IT1032558B publication Critical patent/IT1032558B/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider
IT70707/74A 1973-12-20 1974-12-20 Sistema per generare un multiplon di una frequenza normale IT1032558B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1788973A CH566089A5 (enEXAMPLES) 1973-12-20 1973-12-20

Publications (1)

Publication Number Publication Date
IT1032558B true IT1032558B (it) 1979-06-20

Family

ID=4428858

Family Applications (1)

Application Number Title Priority Date Filing Date
IT70707/74A IT1032558B (it) 1973-12-20 1974-12-20 Sistema per generare un multiplon di una frequenza normale

Country Status (7)

Country Link
JP (1) JPS50115458A (enEXAMPLES)
CH (1) CH566089A5 (enEXAMPLES)
DE (1) DE2456742A1 (enEXAMPLES)
GB (1) GB1452559A (enEXAMPLES)
IT (1) IT1032558B (enEXAMPLES)
NL (1) NL7416281A (enEXAMPLES)
SE (1) SE398423B (enEXAMPLES)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE7411960L (sv) * 1974-09-24 1976-03-25 Fabriker As Haustrups Sett att framstella behallare sasom flaskor eller burkar av polyester
JPS5433983A (en) 1977-08-22 1979-03-13 Toshiba Corp Digital servo device
US4290028A (en) * 1979-07-30 1981-09-15 International Telephone And Telegraph Corporation High speed phase locked loop frequency synthesizer
JPS5720052A (en) 1980-07-11 1982-02-02 Toshiba Corp Input data synchronizing circuit
JPS6051312B2 (ja) * 1981-03-20 1985-11-13 日本ビクター株式会社 水平走査周波数逓倍回路
US4389622A (en) * 1981-09-28 1983-06-21 Honeywell Inc. System for preventing transient induced errors in phase locked loop
JPS58191573A (ja) * 1982-05-06 1983-11-08 Victor Co Of Japan Ltd 水平走査周波数逓倍回路
GB2132042B (en) * 1982-12-15 1986-09-24 British Broadcasting Corp Frequency and timing sources
FR2710806B1 (fr) * 1993-09-28 1995-11-10 France Telecom Dispositif d'asservissement de fréquence.
US5410368A (en) * 1993-12-29 1995-04-25 Zenith Electronics Corp. Carrier acquisition by applying substitute pilot to a synchronous demodulator during a start up interval
IT1278538B1 (it) * 1995-12-20 1997-11-24 Sits Soc It Telecom Siemens Procedimento per il mantenimento dell'aggancio in un pll digitale durante eventuali interruzioni transitorie del segnale sincronizzante
WO1999013582A1 (en) * 1997-09-09 1999-03-18 Advanced Fibre Communications, Inc. Perturbation tolerant digital phase-locked loop employing phase-frequency detector
US8115516B2 (en) 2007-06-14 2012-02-14 Freescale Semiconductor, Inc. Circuit arrangement for filtering unwanted signals from a clock signal, processing system and method of filtering unwanted signals from a clock signal
US8552764B2 (en) 2009-01-05 2013-10-08 Freescale Semiconductor, Inc. Clock glitch detection circuit
WO2010112969A1 (en) 2009-03-31 2010-10-07 Freescale Semiconductor, Inc. Clock glitch detection

Also Published As

Publication number Publication date
NL7416281A (nl) 1975-06-24
SE398423B (sv) 1977-12-19
SE7415990L (enEXAMPLES) 1975-06-23
GB1452559A (en) 1976-10-13
CH566089A5 (enEXAMPLES) 1975-08-29
JPS50115458A (enEXAMPLES) 1975-09-10
DE2456742A1 (de) 1975-06-26

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