IT1024990B - Sistema di memoria ultilizzante una disposizione circuitale di bassa potenza e a controllo dinamico - Google Patents

Sistema di memoria ultilizzante una disposizione circuitale di bassa potenza e a controllo dinamico

Info

Publication number
IT1024990B
IT1024990B IT7053974A IT7053974A IT1024990B IT 1024990 B IT1024990 B IT 1024990B IT 7053974 A IT7053974 A IT 7053974A IT 7053974 A IT7053974 A IT 7053974A IT 1024990 B IT1024990 B IT 1024990B
Authority
IT
Italy
Prior art keywords
control circuit
low power
memory system
circuit arrangement
dynamic control
Prior art date
Application number
IT7053974A
Other languages
English (en)
Italian (it)
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US423297A external-priority patent/US3859545A/en
Priority claimed from US423296A external-priority patent/US3859641A/en
Application filed by Western Electric Co filed Critical Western Electric Co
Application granted granted Critical
Publication of IT1024990B publication Critical patent/IT1024990B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
IT7053974A 1973-12-10 1974-12-05 Sistema di memoria ultilizzante una disposizione circuitale di bassa potenza e a controllo dinamico IT1024990B (it)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US42329573A 1973-12-10 1973-12-10
US423297A US3859545A (en) 1973-12-10 1973-12-10 Low power dynamic control circuitry
US423296A US3859641A (en) 1973-12-10 1973-12-10 Dynamic buffer circuit

Publications (1)

Publication Number Publication Date
IT1024990B true IT1024990B (it) 1978-07-20

Family

ID=27411402

Family Applications (1)

Application Number Title Priority Date Filing Date
IT7053974A IT1024990B (it) 1973-12-10 1974-12-05 Sistema di memoria ultilizzante una disposizione circuitale di bassa potenza e a controllo dinamico

Country Status (5)

Country Link
JP (1) JPS5092053A (enrdf_load_stackoverflow)
DE (1) DE2457992A1 (enrdf_load_stackoverflow)
FR (1) FR2254089A1 (enrdf_load_stackoverflow)
IT (1) IT1024990B (enrdf_load_stackoverflow)
NL (1) NL7415746A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5472934A (en) * 1977-11-24 1979-06-11 Hitachi Ltd Data processor

Also Published As

Publication number Publication date
DE2457992A1 (de) 1975-06-26
JPS5092053A (enrdf_load_stackoverflow) 1975-07-23
FR2254089A1 (en) 1975-07-04
NL7415746A (nl) 1975-06-12

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