IN2015DN03878A - - Google Patents

Info

Publication number
IN2015DN03878A
IN2015DN03878A IN3878DEN2015A IN2015DN03878A IN 2015DN03878 A IN2015DN03878 A IN 2015DN03878A IN 3878DEN2015 A IN3878DEN2015 A IN 3878DEN2015A IN 2015DN03878 A IN2015DN03878 A IN 2015DN03878A
Authority
IN
India
Prior art keywords
cache
memory hierarchy
prefetch
processor
lower level
Prior art date
Application number
Other languages
English (en)
Inventor
John Kalamatianos
Ravindra Nath Bhargava
Ramkumar Jayaseelan
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2015DN03878A publication Critical patent/IN2015DN03878A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN3878DEN2015 2012-11-06 2013-11-05 IN2015DN03878A (cs)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/669,502 US8909866B2 (en) 2012-11-06 2012-11-06 Prefetching to a cache based on buffer fullness
PCT/US2013/068433 WO2014074489A1 (en) 2012-11-06 2013-11-05 Prefetching to a cache based on buffer fullness

Publications (1)

Publication Number Publication Date
IN2015DN03878A true IN2015DN03878A (cs) 2015-10-02

Family

ID=49627073

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3878DEN2015 IN2015DN03878A (cs) 2012-11-06 2013-11-05

Country Status (7)

Country Link
US (1) US8909866B2 (cs)
EP (1) EP2917840B1 (cs)
JP (1) JP6105742B2 (cs)
KR (1) KR101973731B1 (cs)
CN (1) CN104769560B (cs)
IN (1) IN2015DN03878A (cs)
WO (1) WO2014074489A1 (cs)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9749414B2 (en) * 2013-08-29 2017-08-29 International Business Machines Corporation Storing low retention priority data in a dispersed storage network
US9811467B2 (en) * 2014-02-03 2017-11-07 Cavium, Inc. Method and an apparatus for pre-fetching and processing work for procesor cores in a network processor
US9959506B1 (en) * 2014-06-17 2018-05-01 Amazon Technologies, Inc. Predictive content retrieval using device movements
US9558127B2 (en) * 2014-09-09 2017-01-31 Intel Corporation Instruction and logic for a cache prefetcher and dataless fill buffer
WO2017068126A1 (en) * 2015-10-22 2017-04-27 Intervet International B.V. A vaccine to protect an mda positive animal against a disorder arising from an infection with lawsonia intracellularis
US9934149B2 (en) 2016-03-31 2018-04-03 Qualcomm Incorporated Prefetch mechanism for servicing demand miss
US10509732B2 (en) * 2016-04-27 2019-12-17 Advanced Micro Devices, Inc. Selecting cache aging policy for prefetches based on cache test regions
US10073785B2 (en) * 2016-06-13 2018-09-11 Advanced Micro Devices, Inc. Up/down prefetcher
US10353819B2 (en) * 2016-06-24 2019-07-16 Qualcomm Incorporated Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in a processor-based system
CN106487711B (zh) * 2016-10-13 2020-02-21 福建星海通信科技有限公司 一种缓存动态分配的方法以及系统
CN108446240A (zh) * 2016-12-12 2018-08-24 中国航空工业集团公司西安航空计算技术研究所 基于缓存单元id的存储管理电路
US10776043B2 (en) * 2018-08-31 2020-09-15 Arm Limited Storage circuitry request tracking
WO2020102998A1 (zh) * 2018-11-20 2020-05-28 华为技术有限公司 一种删除内存中索引项的方法、装置
WO2021066687A1 (en) * 2019-10-02 2021-04-08 Telefonaktiebolaget Lm Ericsson (Publ) Entities, system and methods performed therein for handling memory operations of an application in a computer environment
US20210182214A1 (en) * 2019-12-17 2021-06-17 Advanced Micro Devices, Inc. Prefetch level demotion
WO2021118645A1 (en) * 2020-05-30 2021-06-17 Futurewei Technologies, Inc. Systems and methods for adaptive hybrid hardware pre-fetch
JP2022107377A (ja) * 2021-01-08 2022-07-21 富士通株式会社 情報処理装置、コンパイル方法、及びコンパイルプログラム
WO2023038657A1 (en) * 2021-09-10 2023-03-16 Purdue Research Foundation Memory management method for pseudo-functional differentiable programming
CN117992364A (zh) * 2024-01-31 2024-05-07 鼎道智芯(上海)半导体有限公司 数据预取方法和装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6065110A (en) * 1998-02-09 2000-05-16 International Business Machines Corporation Method and apparatus for loading an instruction buffer of a processor capable of out-of-order instruction issue
US6212603B1 (en) 1998-04-09 2001-04-03 Institute For The Development Of Emerging Architectures, L.L.C. Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memory
US6029294A (en) * 1998-07-23 2000-02-29 Saringer Research Inc. Mechanism for generating wave motion
JP3512678B2 (ja) * 1999-05-27 2004-03-31 富士通株式会社 キャッシュメモリ制御装置および計算機システム
US6571318B1 (en) 2001-03-02 2003-05-27 Advanced Micro Devices, Inc. Stride based prefetcher with confidence counter and dynamic prefetch-ahead mechanism
US20040103251A1 (en) * 2002-11-26 2004-05-27 Mitchell Alsup Microprocessor including a first level cache and a second level cache having different cache line sizes
US20060143401A1 (en) * 2004-12-27 2006-06-29 Jacob Doweck Method and apparatus for prefetching based on cache fill buffer hits
US7840761B2 (en) * 2005-04-01 2010-11-23 Stmicroelectronics, Inc. Apparatus and method for supporting execution of prefetch threads
JP4574712B2 (ja) * 2006-02-28 2010-11-04 富士通株式会社 演算処理装置、情報処理装置及び制御方法
US7908236B2 (en) * 2006-07-20 2011-03-15 International Business Machines Corporation Using multiple data structures to manage data in cache
US7484042B2 (en) * 2006-08-18 2009-01-27 International Business Machines Corporation Data processing system and method for predictively selecting a scope of a prefetch operation
US8230177B2 (en) * 2009-05-28 2012-07-24 Oracle America, Inc. Store prefetching via store queue lookahead
JP5444889B2 (ja) * 2009-06-30 2014-03-19 富士通株式会社 演算処理装置および演算処理装置の制御方法
CN101634970B (zh) * 2009-08-26 2011-09-07 成都市华为赛门铁克科技有限公司 预取长度调整方法、装置和存储系统
US8856451B2 (en) 2010-08-26 2014-10-07 Advanced Micro Devices, Inc. Method and apparatus for adapting aggressiveness of a pre-fetcher
US8880847B2 (en) * 2010-09-28 2014-11-04 Texas Instruments Incorporated Multistream prefetch buffer

Also Published As

Publication number Publication date
WO2014074489A1 (en) 2014-05-15
JP6105742B2 (ja) 2017-03-29
US20140129772A1 (en) 2014-05-08
US8909866B2 (en) 2014-12-09
CN104769560B (zh) 2017-04-12
KR101973731B1 (ko) 2019-04-29
EP2917840B1 (en) 2018-12-26
JP2016509272A (ja) 2016-03-24
KR20150082457A (ko) 2015-07-15
EP2917840A1 (en) 2015-09-16
CN104769560A (zh) 2015-07-08

Similar Documents

Publication Publication Date Title
IN2015DN03878A (cs)
IN2012DN02977A (cs)
JP7337173B2 (ja) トランスレーションルックアサイドバッファエビクションに基づくキャッシュ置換
GB201303300D0 (en) Data Processing
KR101483849B1 (ko) 계층적으로 캐싱되는 프로세서들에서의 조정된 프리페칭
KR101497371B1 (ko) 퍼지 스트라이드 프리페치 방법 및 장치
CN106537362B (zh) 数据处理装置和在数据处理装置中处理地址转换的方法
JP6696987B2 (ja) 仮想アドレスを使用してアクセスされるキャッシュ
JP6279508B2 (ja) 事前充填能力を有するメモリ管理ユニット
US9223710B2 (en) Read-write partitioning of cache memory
EP3657338B1 (en) Data caching
WO2017211240A1 (zh) 一种处理器芯片以及指令缓存的预取方法
GB201303302D0 (en) Data processing
US20170161194A1 (en) Page-based prefetching triggered by tlb activity
US20160224467A1 (en) Hierarchical cache structure and handling thereof
US20110072218A1 (en) Prefetch promotion mechanism to reduce cache pollution
KR20160122278A (ko) 프리페칭을 갖는 변환 색인 버퍼
IN2015DN01261A (cs)
JP2018504694A5 (cs)
CN109074314A (zh) 基于存储器请求大小的预测减少存储器访问带宽
MX2009007940A (es) Filtrado por rastreo mediante el uso de una cache de solicitud de rastreo.
JP2013519965A5 (cs)
JP2016520916A (ja) クロスページプリフェッチングの方法、装置、およびシステム
KR20160033154A (ko) 프로세서에 대한 액세스 맵-패턴 매치 기반 프리페치 유닛
US20230205872A1 (en) Method and apparatus to address row hammer attacks at a host processor