MX2009007940A - Filtrado por rastreo mediante el uso de una cache de solicitud de rastreo. - Google Patents

Filtrado por rastreo mediante el uso de una cache de solicitud de rastreo.

Info

Publication number
MX2009007940A
MX2009007940A MX2009007940A MX2009007940A MX2009007940A MX 2009007940 A MX2009007940 A MX 2009007940A MX 2009007940 A MX2009007940 A MX 2009007940A MX 2009007940 A MX2009007940 A MX 2009007940A MX 2009007940 A MX2009007940 A MX 2009007940A
Authority
MX
Mexico
Prior art keywords
snoop
cache
processor
identification
lookup
Prior art date
Application number
MX2009007940A
Other languages
English (en)
Inventor
James Norris Dieffenderfer
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2009007940A publication Critical patent/MX2009007940A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Una caché de solicitud de rastreo mantiene registros de solicitudes de rastreo emitidas previamente. Luego de escribir los datos compartidos, una entidad de rastreo realiza una consulta en la caché. Si la consulta es un acierto (y, en algunas modalidades, incluye una identificación de un procesador designado), la entidad de rastreo suprime la solicitud de rastreo. Si la consulta es un desacierto (o aciertos pero la entrada de aciertos carece de una identificación del procesador designado) la entidad de rastreo asigna una entrada en la caché (o acciona una identificación del procesador designado) y dirige una solicitud de rastreo tal que el procesador designado, cambie el estado de una línea correspondiente en la caché Li del procesador. Cuando el procesador lee los datos compartidos, realiza una consulta de solicitud de rastreo a la caché, e invalida una entrada de aciertos en el caso de un acierto (o borra la identificación del procesador de la línea de aciertos) para que las otras entidades de rastreo no supriman las solicitudes de rastreo.
MX2009007940A 2007-01-26 2008-01-28 Filtrado por rastreo mediante el uso de una cache de solicitud de rastreo. MX2009007940A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/627,705 US20080183972A1 (en) 2007-01-26 2007-01-26 Snoop Filtering Using a Snoop Request Cache
PCT/US2008/052216 WO2008092159A1 (en) 2007-01-26 2008-01-28 Snoop filtering using a snoop request cache

Publications (1)

Publication Number Publication Date
MX2009007940A true MX2009007940A (es) 2009-08-18

Family

ID=39512520

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2009007940A MX2009007940A (es) 2007-01-26 2008-01-28 Filtrado por rastreo mediante el uso de una cache de solicitud de rastreo.

Country Status (10)

Country Link
US (1) US20080183972A1 (es)
EP (1) EP2115597A1 (es)
JP (1) JP5221565B2 (es)
KR (2) KR101313710B1 (es)
CN (1) CN101601019B (es)
BR (1) BRPI0807437A2 (es)
CA (1) CA2674723A1 (es)
MX (1) MX2009007940A (es)
RU (1) RU2443011C2 (es)
WO (1) WO2008092159A1 (es)

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US8250307B2 (en) * 2008-02-01 2012-08-21 International Business Machines Corporation Sourcing differing amounts of prefetch data in response to data prefetch requests
US8117401B2 (en) * 2008-02-01 2012-02-14 International Business Machines Corporation Interconnect operation indicating acceptability of partial data delivery
US8024527B2 (en) * 2008-02-01 2011-09-20 International Business Machines Corporation Partial cache line accesses based on memory access patterns
US8140771B2 (en) * 2008-02-01 2012-03-20 International Business Machines Corporation Partial cache line storage-modifying operation based upon a hint
US8266381B2 (en) 2008-02-01 2012-09-11 International Business Machines Corporation Varying an amount of data retrieved from memory based upon an instruction hint
US8423721B2 (en) * 2008-04-30 2013-04-16 Freescale Semiconductor, Inc. Cache coherency protocol in a data processing system
US8706974B2 (en) * 2008-04-30 2014-04-22 Freescale Semiconductor, Inc. Snoop request management in a data processing system
US8762652B2 (en) * 2008-04-30 2014-06-24 Freescale Semiconductor, Inc. Cache coherency protocol in a data processing system
US9158692B2 (en) * 2008-08-12 2015-10-13 International Business Machines Corporation Cache injection directing technique
US8868847B2 (en) * 2009-03-11 2014-10-21 Apple Inc. Multi-core processor snoop filtering
US8117390B2 (en) 2009-04-15 2012-02-14 International Business Machines Corporation Updating partial cache lines in a data processing system
US8140759B2 (en) 2009-04-16 2012-03-20 International Business Machines Corporation Specifying an access hint for prefetching partial cache block data in a cache hierarchy
US8856456B2 (en) 2011-06-09 2014-10-07 Apple Inc. Systems, methods, and devices for cache block coherence
US9477600B2 (en) 2011-08-08 2016-10-25 Arm Limited Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode
KR101996351B1 (ko) 2012-06-15 2019-07-05 인텔 코포레이션 통합된 구조를 갖는 동적 디스패치 윈도우를 가지는 가상 load store 큐
KR101996592B1 (ko) 2012-06-15 2019-07-04 인텔 코포레이션 명확화 없는 비순차 load store 큐를 갖는 재정렬된 투기적 명령어 시퀀스들
CN104583943B (zh) 2012-06-15 2018-06-08 英特尔公司 拥有具有分布式结构的动态分派窗口的虚拟加载存储队列
CN104583975B (zh) 2012-06-15 2017-07-14 英特尔公司 无消歧乱序加载存储队列
CN104583956B (zh) 2012-06-15 2019-01-04 英特尔公司 用于实现加载存储重新排序和优化的指令定义
EP2862084A4 (en) 2012-06-15 2016-11-30 Soft Machines Inc METHOD AND SYSTEM FOR IMPLEMENTING RECOVERY FROM A SPECULATIVE TRANSMISSION OF FAULT FORECASTS / ERRORS DUE TO THE CHANGE AND OPTIMIZATION OF MEMORY LOADS
US9268697B2 (en) * 2012-12-29 2016-02-23 Intel Corporation Snoop filter having centralized translation circuitry and shadow tag array
US20160110113A1 (en) * 2014-10-17 2016-04-21 Texas Instruments Incorporated Memory Compression Operable for Non-contiguous write/read Addresses
US9575893B2 (en) * 2014-10-22 2017-02-21 Mediatek Inc. Snoop filter for multi-processor system and related snoop filtering method
JP6334824B2 (ja) * 2015-07-16 2018-05-30 東芝メモリ株式会社 メモリコントローラ、情報処理装置および処理装置
US10157133B2 (en) * 2015-12-10 2018-12-18 Arm Limited Snoop filter for cache coherency in a data processing system
US9898408B2 (en) * 2016-04-01 2018-02-20 Intel Corporation Sharing aware snoop filter apparatus and method
US10360158B2 (en) 2017-03-27 2019-07-23 Samsung Electronics Co., Ltd. Snoop filter with stored replacement information, method for same, and system including victim exclusive cache and snoop filter shared replacement policies
KR20220083522A (ko) 2020-12-11 2022-06-20 윤태진 세척이 용이한 개폐형 싱크대 음식물 거름망
US11983538B2 (en) * 2022-04-18 2024-05-14 Cadence Design Systems, Inc. Load-store unit dual tags and replays

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RU2189630C1 (ru) * 2001-11-21 2002-09-20 Бабаян Борис Арташесович Способ фильтрации межпроцессорных запросов в многопроцессорных вычислительных системах и устройство для его осуществления
US6985972B2 (en) * 2002-10-03 2006-01-10 International Business Machines Corporation Dynamic cache coherency snooper presence with variable snoop latency
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US7392351B2 (en) * 2005-03-29 2008-06-24 International Business Machines Corporation Method and apparatus for filtering snoop requests using stream registers

Also Published As

Publication number Publication date
US20080183972A1 (en) 2008-07-31
RU2009132090A (ru) 2011-03-10
KR20120055739A (ko) 2012-05-31
KR101313710B1 (ko) 2013-10-01
CA2674723A1 (en) 2008-07-31
WO2008092159A1 (en) 2008-07-31
EP2115597A1 (en) 2009-11-11
CN101601019A (zh) 2009-12-09
BRPI0807437A2 (pt) 2014-07-01
CN101601019B (zh) 2013-07-24
KR20090110920A (ko) 2009-10-23
JP2010517184A (ja) 2010-05-20
RU2443011C2 (ru) 2012-02-20
JP5221565B2 (ja) 2013-06-26

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