IN2014CN03371A - - Google Patents

Info

Publication number
IN2014CN03371A
IN2014CN03371A IN3371CHN2014A IN2014CN03371A IN 2014CN03371 A IN2014CN03371 A IN 2014CN03371A IN 3371CHN2014 A IN3371CHN2014 A IN 3371CHN2014A IN 2014CN03371 A IN2014CN03371 A IN 2014CN03371A
Authority
IN
India
Prior art keywords
data
stored
video data
conducted
compression
Prior art date
Application number
Other languages
English (en)
Inventor
Zhen Fang
Nitin B Gupte
Xiaowei Jiang
Original Assignee
Intel Corporationu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporationu filed Critical Intel Corporationu
Publication of IN2014CN03371A publication Critical patent/IN2014CN03371A/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H04N19/426—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements using memory downsizing methods
    • H04N19/428—Recompression, e.g. by spatial or temporal decimation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/503—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
    • H04N19/51—Motion estimation or motion compensation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/79—Processing of colour television signals in connection with recording
    • H04N9/80—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback
    • H04N9/804—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components
    • H04N9/8042—Transformation of the television signal for recording, e.g. modulation, frequency changing; Inverse transformation for playback involving pulse code modulation of the colour picture signal components involving data reduction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
IN3371CHN2014 2011-12-21 2011-12-21 IN2014CN03371A (tr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/066556 WO2013095448A1 (en) 2011-12-21 2011-12-21 Dram compression scheme to reduce power consumption in motion compensation and display refresh

Publications (1)

Publication Number Publication Date
IN2014CN03371A true IN2014CN03371A (tr) 2015-07-03

Family

ID=48638976

Family Applications (1)

Application Number Title Priority Date Filing Date
IN3371CHN2014 IN2014CN03371A (tr) 2011-12-21 2011-12-21

Country Status (9)

Country Link
US (1) US9268723B2 (tr)
EP (1) EP2795896A4 (tr)
JP (1) JP5639144B2 (tr)
KR (2) KR101605047B1 (tr)
CN (1) CN103179393B (tr)
IN (1) IN2014CN03371A (tr)
RU (1) RU2599959C2 (tr)
TW (1) TWI524326B (tr)
WO (1) WO2013095448A1 (tr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9268723B2 (en) 2011-12-21 2016-02-23 Intel Corporation Dram compression scheme to reduce power consumption in motion compensation and display refresh
US20140355665A1 (en) * 2013-05-31 2014-12-04 Altera Corporation Adaptive Video Reference Frame Compression with Control Elements
US9864536B2 (en) 2013-10-24 2018-01-09 Qualcomm Incorporated System and method for conserving power consumption in a memory system
US20150121111A1 (en) * 2013-10-24 2015-04-30 Qualcomm Incorporated System and method for providing multi-user power saving codebook optmization
US10080028B2 (en) 2014-11-26 2018-09-18 Samsung Display Co., Ltd. System and method of compensating for image compression errors
KR102373544B1 (ko) 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
US9721640B2 (en) * 2015-12-09 2017-08-01 Intel Corporation Performance of additional refresh operations during self-refresh mode
US10168909B1 (en) * 2016-03-29 2019-01-01 Amazon Technologies, Inc. Compression hardware acceleration
CN110457235B (zh) * 2019-08-20 2021-10-08 Oppo广东移动通信有限公司 内存压缩方法、装置、终端及存储介质

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW224553B (en) * 1993-03-01 1994-06-01 Sony Co Ltd Method and apparatus for inverse discrete consine transform and coding/decoding of moving picture
JPH08116539A (ja) 1994-10-17 1996-05-07 Hitachi Ltd 動画像符号化装置と動画像符号化方法
US5812791A (en) * 1995-05-10 1998-09-22 Cagent Technologies, Inc. Multiple sequence MPEG decoder
US5847762A (en) 1995-12-27 1998-12-08 Thomson Consumer Electronics, Inc. MPEG system which decompresses and then recompresses MPEG video data before storing said recompressed MPEG video data into memory
US5668599A (en) * 1996-03-19 1997-09-16 International Business Machines Corporation Memory management for an MPEG2 compliant decoder
US6157740A (en) * 1997-11-17 2000-12-05 International Business Machines Corporation Compression/decompression engine for enhanced memory storage in MPEG decoder
US6278735B1 (en) 1998-03-19 2001-08-21 International Business Machines Corporation Real-time single pass variable bit rate control strategy and encoder
US6628714B1 (en) * 1998-12-18 2003-09-30 Zenith Electronics Corporation Down converting MPEG encoded high definition sequences to lower resolution with reduced memory in decoder loop
US6510178B1 (en) 1999-12-15 2003-01-21 Zenith Electronics Corporation Compensating for drift in the down conversion of high definition sequences to lower resolution sequences
US20020176507A1 (en) * 2001-03-26 2002-11-28 Mediatek Inc. Method and an apparatus for reordering a decoded picture sequence using virtual picture
KR100598093B1 (ko) * 2003-01-29 2006-07-07 삼성전자주식회사 낮은 메모리 대역폭을 갖는 동영상 압축 장치와 그 방법
KR100771401B1 (ko) 2005-08-01 2007-10-30 (주)펄서스 테크놀러지 프로그래머블 프로세서에서 ｍｐｅｇ-2 또는 ｍｐｅｇ-4ａａｃ 오디오 복호 알고리즘을 처리하기 위한 연산 회로및 연산 방법
JP4384130B2 (ja) * 2006-03-28 2009-12-16 株式会社東芝 動画像復号方法及び装置
JP5245794B2 (ja) 2008-12-15 2013-07-24 富士通株式会社 画像処理装置および方法
JP5504885B2 (ja) 2009-12-25 2014-05-28 富士通株式会社 画像処理装置および画像処理方法
US9268723B2 (en) 2011-12-21 2016-02-23 Intel Corporation Dram compression scheme to reduce power consumption in motion compensation and display refresh

Also Published As

Publication number Publication date
JP5639144B2 (ja) 2014-12-10
WO2013095448A1 (en) 2013-06-27
EP2795896A4 (en) 2015-05-20
CN103179393A (zh) 2013-06-26
US9268723B2 (en) 2016-02-23
KR101605047B1 (ko) 2016-03-21
KR20150081373A (ko) 2015-07-13
KR20140099501A (ko) 2014-08-12
CN103179393B (zh) 2016-08-24
TW201404158A (zh) 2014-01-16
JP2013132056A (ja) 2013-07-04
RU2599959C2 (ru) 2016-10-20
RU2014126348A (ru) 2016-01-27
TWI524326B (zh) 2016-03-01
US20140204105A1 (en) 2014-07-24
EP2795896A1 (en) 2014-10-29

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