IL33796A - Data processor interrupt system - Google Patents

Data processor interrupt system

Info

Publication number
IL33796A
IL33796A IL33796A IL3379670A IL33796A IL 33796 A IL33796 A IL 33796A IL 33796 A IL33796 A IL 33796A IL 3379670 A IL3379670 A IL 3379670A IL 33796 A IL33796 A IL 33796A
Authority
IL
Israel
Prior art keywords
interrupt
storage means
discrete
interrupt condition
level
Prior art date
Application number
IL33796A
Other languages
English (en)
Other versions
IL33796A0 (en
Original Assignee
Sanders Associates Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanders Associates Inc filed Critical Sanders Associates Inc
Publication of IL33796A0 publication Critical patent/IL33796A0/xx
Publication of IL33796A publication Critical patent/IL33796A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
IL33796A 1969-02-10 1970-01-28 Data processor interrupt system IL33796A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US79803369A 1969-02-10 1969-02-10

Publications (2)

Publication Number Publication Date
IL33796A0 IL33796A0 (en) 1970-03-22
IL33796A true IL33796A (en) 1972-06-28

Family

ID=25172359

Family Applications (1)

Application Number Title Priority Date Filing Date
IL33796A IL33796A (en) 1969-02-10 1970-01-28 Data processor interrupt system

Country Status (5)

Country Link
US (1) US3611305A (de)
DE (1) DE2005813A1 (de)
FR (1) FR2032848A5 (de)
GB (1) GB1299962A (de)
IL (1) IL33796A (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2028345C3 (de) * 1970-06-09 1981-04-09 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Verteilung von Ablaufanforderungen in einer programmgesteuerten Datenvermittlungsanlage
US3735357A (en) * 1970-09-18 1973-05-22 Ibm Priority system for a communication control unit
IT971304B (it) * 1972-11-29 1974-04-30 Honeywell Inf Systems Sistema di accesso a priorita variabile dinamicamente
US3921150A (en) * 1974-09-12 1975-11-18 Sperry Rand Corp Three-rank priority select register system for fail-safe priority determination
JPS5226124A (en) * 1975-08-22 1977-02-26 Fujitsu Ltd Buffer memory control unit
DE2659662C3 (de) * 1976-12-30 1981-10-08 Ibm Deutschland Gmbh, 7000 Stuttgart Prioritätsstufengesteuerte Unterbrechungseinrichtung
IT1100916B (it) * 1978-11-06 1985-09-28 Honeywell Inf Systems Apparato per gestione di richieste di trasferimento dati in sistemi di elaborazione dati
FR2646941B1 (fr) * 1989-05-10 1991-07-05 Lapersonne Joseph Dispositif pour gerer et arbitrer des impulsions d'interruption aleatoires declenchant des programmes dans un microprocesseur
KR920003152A (ko) * 1990-07-31 1992-02-29 이헌조 다중 인터럽트 처리회로
US5831877A (en) * 1995-05-26 1998-11-03 National Semiconductor Corporation Bit searching through 8, 16, or 32 bit operands using a 32 bit data path
US5764996A (en) * 1995-11-27 1998-06-09 Digital Equipment Corporation Method and apparatus for optimizing PCI interrupt binding and associated latency in extended/bridged PCI busses
US5898694A (en) * 1996-12-30 1999-04-27 Cabletron Systems, Inc. Method of round robin bus arbitration
JP6056576B2 (ja) * 2013-03-18 2017-01-11 富士通株式会社 割り込み要因を特定する方法及び装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3289168A (en) * 1962-07-31 1966-11-29 Ibm Interrupt control system
US3309672A (en) * 1963-01-04 1967-03-14 Sylvania Electric Prod Electronic computer interrupt system
US3473156A (en) * 1964-05-04 1969-10-14 Gen Electric Data processing unit for providing sequential memory access and record thereof under control of external apparatus
US3331055A (en) * 1964-06-01 1967-07-11 Sperry Rand Corp Data communication system with matrix selection of line terminals
US3434111A (en) * 1966-06-29 1969-03-18 Electronic Associates Program interrupt system

Also Published As

Publication number Publication date
FR2032848A5 (de) 1970-11-27
GB1299962A (en) 1972-12-13
IL33796A0 (en) 1970-03-22
DE2005813A1 (de) 1970-09-03
US3611305A (en) 1971-10-05

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