IL145651A0 - Status bits for cache memory - Google Patents

Status bits for cache memory

Info

Publication number
IL145651A0
IL145651A0 IL14565100A IL14565100A IL145651A0 IL 145651 A0 IL145651 A0 IL 145651A0 IL 14565100 A IL14565100 A IL 14565100A IL 14565100 A IL14565100 A IL 14565100A IL 145651 A0 IL145651 A0 IL 145651A0
Authority
IL
Israel
Prior art keywords
cache memory
status bits
bits
status
cache
Prior art date
Application number
IL14565100A
Other languages
English (en)
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of IL145651A0 publication Critical patent/IL145651A0/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IL14565100A 1999-06-08 2000-02-04 Status bits for cache memory IL145651A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9913348A GB2350910A (en) 1999-06-08 1999-06-08 Status bits for cache memory
PCT/GB2000/000335 WO2000075785A1 (en) 1999-06-08 2000-02-04 Status bits for cache memory

Publications (1)

Publication Number Publication Date
IL145651A0 true IL145651A0 (en) 2002-06-30

Family

ID=10854970

Family Applications (2)

Application Number Title Priority Date Filing Date
IL14565100A IL145651A0 (en) 1999-06-08 2000-02-04 Status bits for cache memory
IL145651A IL145651A (en) 1999-06-08 2001-09-25 Bit Cache Mode (BITS)

Family Applications After (1)

Application Number Title Priority Date Filing Date
IL145651A IL145651A (en) 1999-06-08 2001-09-25 Bit Cache Mode (BITS)

Country Status (12)

Country Link
US (1) US6272033B1 (ru)
EP (1) EP1190325B1 (ru)
JP (1) JP2003501744A (ru)
KR (1) KR100606873B1 (ru)
CN (1) CN1145887C (ru)
DE (1) DE60003426T2 (ru)
GB (1) GB2350910A (ru)
IL (2) IL145651A0 (ru)
MY (1) MY120377A (ru)
RU (1) RU2237278C2 (ru)
TW (1) TW507124B (ru)
WO (1) WO2000075785A1 (ru)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2369690B (en) * 2000-11-29 2002-10-16 Sun Microsystems Inc Enhanced protection for memory modification tracking
GB2369694B (en) * 2000-11-29 2002-10-16 Sun Microsystems Inc Efficient memory modification tracking
GB2369691B (en) * 2000-11-29 2003-06-04 Sun Microsystems Inc Control logic for memory modification tracking
US6965970B2 (en) * 2001-09-27 2005-11-15 Intel Corporation List based method and apparatus for selective and rapid cache flushes
JP4434534B2 (ja) * 2001-09-27 2010-03-17 株式会社東芝 プロセッサ・システム
US7412433B2 (en) * 2002-11-19 2008-08-12 International Business Machines Corporation Hierarchical storage management using dynamic tables of contents and sets of tables of contents
US20040199723A1 (en) * 2003-04-03 2004-10-07 Shelor Charles F. Low-power cache and method for operating same
US7674671B2 (en) * 2004-12-13 2010-03-09 Optomec Design Company Aerodynamic jetting of aerosolized fluids for fabrication of passive structures
CN101021858A (zh) * 2007-01-29 2007-08-22 华为技术有限公司 一种数据存储方法及装置及数据查找、添加、删除方法
US7685181B2 (en) * 2007-02-26 2010-03-23 International Business Machines Corporation Method and system for utilizing a hierarchical bitmap structure to provide a fast and reliable mechanism to represent large deleted data sets in relational databases
JP2008234074A (ja) * 2007-03-16 2008-10-02 Fujitsu Ltd キャッシュ装置
US8347029B2 (en) * 2007-12-28 2013-01-01 Intel Corporation Systems and methods for fast state modification of at least a portion of non-volatile memory
US20090300293A1 (en) * 2008-05-30 2009-12-03 Advanced Micro Devices, Inc. Dynamically Partitionable Cache
CN102571569B (zh) * 2011-12-28 2015-04-01 方正国际软件有限公司 一种报文预知方法及系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4426682A (en) * 1981-05-22 1984-01-17 Harris Corporation Fast cache flush mechanism
DE3919802C2 (de) * 1988-06-17 1997-01-30 Hitachi Ltd Speichersteuersystem für ein Multiprozessorsystem
US5539894A (en) * 1993-04-20 1996-07-23 Sun Microsystems, Inc. Method and apparatus for optimizing a sector cache tag, block and sub-block structure base on main memory size
US5568416A (en) * 1994-03-24 1996-10-22 Kawasaki Steel Corporation Associative memory
DE19516949A1 (de) * 1994-05-11 1996-02-15 Gmd Gmbh Speichervorrichtung zum Speichern von Daten
US6046923A (en) * 1999-01-13 2000-04-04 Lucent Technologies Inc. Content-addressable memory architecture with column muxing

Also Published As

Publication number Publication date
IL145651A (en) 2006-10-05
US6272033B1 (en) 2001-08-07
GB2350910A (en) 2000-12-13
EP1190325A1 (en) 2002-03-27
EP1190325B1 (en) 2003-06-18
TW507124B (en) 2002-10-21
RU2237278C2 (ru) 2004-09-27
JP2003501744A (ja) 2003-01-14
WO2000075785A1 (en) 2000-12-14
DE60003426T2 (de) 2004-05-19
CN1355901A (zh) 2002-06-26
MY120377A (en) 2005-10-31
KR20020010922A (ko) 2002-02-06
CN1145887C (zh) 2004-04-14
KR100606873B1 (ko) 2006-07-31
GB9913348D0 (en) 1999-08-11
DE60003426D1 (de) 2003-07-24

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