IL134460A0 - Data processor with parallel decoding and execution of data and address instructions - Google Patents
Data processor with parallel decoding and execution of data and address instructionsInfo
- Publication number
- IL134460A0 IL134460A0 IL13446098A IL13446098A IL134460A0 IL 134460 A0 IL134460 A0 IL 134460A0 IL 13446098 A IL13446098 A IL 13446098A IL 13446098 A IL13446098 A IL 13446098A IL 134460 A0 IL134460 A0 IL 134460A0
- Authority
- IL
- Israel
- Prior art keywords
- data
- execution
- parallel decoding
- address instructions
- data processor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30141—Implementation provisions of register files, e.g. ports
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
- G06F9/381—Loop buffering
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3856—Reordering of instructions, e.g. using queues or age tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
- G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/928,766 US6076159A (en) | 1997-09-12 | 1997-09-12 | Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline |
PCT/US1998/018575 WO1999014666A2 (fr) | 1997-09-12 | 1998-09-04 | Processeur de donnees a decodage et execution en parallele d'instructions de donnees et d'adresses |
Publications (1)
Publication Number | Publication Date |
---|---|
IL134460A0 true IL134460A0 (en) | 2001-04-30 |
Family
ID=25456715
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IL13446098A IL134460A0 (en) | 1997-09-12 | 1998-09-04 | Data processor with parallel decoding and execution of data and address instructions |
Country Status (7)
Country | Link |
---|---|
US (1) | US6076159A (fr) |
EP (3) | EP1455271B1 (fr) |
JP (1) | JP2001516918A (fr) |
KR (1) | KR20010023914A (fr) |
DE (1) | DE69821957T2 (fr) |
IL (1) | IL134460A0 (fr) |
WO (1) | WO1999014666A2 (fr) |
Families Citing this family (56)
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US7114056B2 (en) * | 1998-12-03 | 2006-09-26 | Sun Microsystems, Inc. | Local and global register partitioning in a VLIW processor |
US7117342B2 (en) * | 1998-12-03 | 2006-10-03 | Sun Microsystems, Inc. | Implicitly derived register specifiers in a processor |
US6615338B1 (en) * | 1998-12-03 | 2003-09-02 | Sun Microsystems, Inc. | Clustered architecture in a VLIW processor |
US6260133B1 (en) * | 1999-02-08 | 2001-07-10 | Kabushiki Kaisha Toshiba | Processor having operating instruction which uses operation units in different pipelines simultaneously |
US6237066B1 (en) * | 1999-03-22 | 2001-05-22 | Sun Microsystems, Inc. | Supporting multiple outstanding requests to multiple targets in a pipelined memory system |
EP1050807A1 (fr) * | 1999-05-03 | 2000-11-08 | Sgs Thomson Microelectronics Sa | Accès à mémoire dans une mémoire d'ordinateur |
EP1050809A1 (fr) * | 1999-05-03 | 2000-11-08 | STMicroelectronics SA | Dépendence d'instruction d'ordinateur |
EP1050808B1 (fr) * | 1999-05-03 | 2008-04-30 | STMicroelectronics S.A. | Délivrance d'instructions d'ordinateur |
EP1050818A1 (fr) * | 1999-05-03 | 2000-11-08 | STMicroelectronics SA | Accès en mémoire d'ordinateur |
US6393551B1 (en) * | 1999-05-26 | 2002-05-21 | Infineon Technologies North America Corp. | Reducing instruction transactions in a microprocessor |
US7302557B1 (en) * | 1999-12-27 | 2007-11-27 | Impact Technologies, Inc. | Method and apparatus for modulo scheduled loop execution in a processor architecture |
US6567895B2 (en) * | 2000-05-31 | 2003-05-20 | Texas Instruments Incorporated | Loop cache memory and cache controller for pipelined microprocessors |
US6748523B1 (en) * | 2000-11-02 | 2004-06-08 | Intel Corporation | Hardware loops |
US7472259B2 (en) * | 2000-12-06 | 2008-12-30 | Analog Devices, Inc. | Multi-cycle instructions |
US7069545B2 (en) * | 2000-12-29 | 2006-06-27 | Intel Corporation | Quantization and compression for computation reuse |
GB2381602B (en) | 2001-10-12 | 2004-04-14 | Siroyan Ltd | Early resolving instructions |
US6948162B2 (en) * | 2002-01-09 | 2005-09-20 | Sun Microsystems, Inc. | Enhanced parallelism in trace scheduling by using renaming |
US20030154363A1 (en) * | 2002-02-11 | 2003-08-14 | Soltis Donald C. | Stacked register aliasing in data hazard detection to reduce circuit |
KR100491323B1 (ko) * | 2002-03-13 | 2005-05-24 | (주) 네오시스트 | 독립 파이프라인에 의한 저장 방식을 갖는 전자 계산기 |
AU2003263491A1 (en) * | 2002-10-11 | 2004-05-04 | Koninklijke Philips Electronics N.V. | Vliw processor with instruction address modification |
US7159103B2 (en) * | 2003-03-24 | 2007-01-02 | Infineon Technologies Ag | Zero-overhead loop operation in microprocessor having instruction buffer |
CN101221494B (zh) * | 2005-08-31 | 2010-12-29 | 上海海尔集成电路有限公司 | 一种8位risc微控制器构架 |
US7711934B2 (en) * | 2005-10-31 | 2010-05-04 | Mips Technologies, Inc. | Processor core and method for managing branch misprediction in an out-of-order processor pipeline |
US7734901B2 (en) * | 2005-10-31 | 2010-06-08 | Mips Technologies, Inc. | Processor core and method for managing program counter redirection in an out-of-order processor pipeline |
US7873820B2 (en) * | 2005-11-15 | 2011-01-18 | Mips Technologies, Inc. | Processor utilizing a loop buffer to reduce power consumption |
US7496771B2 (en) * | 2005-11-15 | 2009-02-24 | Mips Technologies, Inc. | Processor accessing a scratch pad on-demand to reduce power consumption |
US7562191B2 (en) * | 2005-11-15 | 2009-07-14 | Mips Technologies, Inc. | Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme |
KR100717055B1 (ko) | 2005-11-18 | 2007-05-10 | 삼성전자주식회사 | Cabac 복호기에서 복수의 이진 값들을 파이프라인방식에 의하여 복호화하는 방법 및 이를 위한 복호화 장치 |
US7721071B2 (en) * | 2006-02-28 | 2010-05-18 | Mips Technologies, Inc. | System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor |
US20070204139A1 (en) | 2006-02-28 | 2007-08-30 | Mips Technologies, Inc. | Compact linked-list-based multi-threaded instruction graduation buffer |
US20080016326A1 (en) | 2006-07-14 | 2008-01-17 | Mips Technologies, Inc. | Latest producer tracking in an out-of-order processor, and applications thereof |
US7370178B1 (en) | 2006-07-14 | 2008-05-06 | Mips Technologies, Inc. | Method for latest producer tracking in an out-of-order processor, and applications thereof |
US7681022B2 (en) * | 2006-07-25 | 2010-03-16 | Qualcomm Incorporated | Efficient interrupt return address save mechanism |
US7657708B2 (en) * | 2006-08-18 | 2010-02-02 | Mips Technologies, Inc. | Methods for reducing data cache access power in a processor using way selection bits |
US7650465B2 (en) | 2006-08-18 | 2010-01-19 | Mips Technologies, Inc. | Micro tag array having way selection bits for reducing data cache access power |
US8032734B2 (en) * | 2006-09-06 | 2011-10-04 | Mips Technologies, Inc. | Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor |
US7647475B2 (en) * | 2006-09-06 | 2010-01-12 | Mips Technologies, Inc. | System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue |
US9946547B2 (en) | 2006-09-29 | 2018-04-17 | Arm Finance Overseas Limited | Load/store unit for a processor, and applications thereof |
US7594079B2 (en) * | 2006-09-29 | 2009-09-22 | Mips Technologies, Inc. | Data cache virtual hint way prediction, and applications thereof |
US8078846B2 (en) | 2006-09-29 | 2011-12-13 | Mips Technologies, Inc. | Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated |
US20080082793A1 (en) * | 2006-09-29 | 2008-04-03 | Mips Technologies, Inc. | Detection and prevention of write-after-write hazards, and applications thereof |
US7769987B2 (en) | 2007-06-27 | 2010-08-03 | International Business Machines Corporation | Single hot forward interconnect scheme for delayed execution pipelines |
WO2009000624A1 (fr) * | 2007-06-27 | 2008-12-31 | International Business Machines Corporation | Transfert de données dans un processeur |
US7984272B2 (en) | 2007-06-27 | 2011-07-19 | International Business Machines Corporation | Design structure for single hot forward interconnect scheme for delayed execution pipelines |
US7822948B2 (en) * | 2008-01-03 | 2010-10-26 | International Business Machines Corporation | Apparatus, system, and method for discontiguous multiple issue of instructions |
US20100122066A1 (en) * | 2008-11-12 | 2010-05-13 | Freescale Semiconductor, Inc. | Instruction method for facilitating efficient coding and instruction fetch of loop construct |
US9170816B2 (en) * | 2009-01-15 | 2015-10-27 | Altair Semiconductor Ltd. | Enhancing processing efficiency in large instruction width processors |
GB2466984B (en) | 2009-01-16 | 2011-07-27 | Imagination Tech Ltd | Multi-threaded data processing system |
JP5590849B2 (ja) * | 2009-10-08 | 2014-09-17 | キヤノン株式会社 | 複数の処理モジュールを有する並列処理回路を備えるデータ処理装置、その制御装置、およびその制御方法、プログラム |
GB2485538B (en) * | 2010-11-16 | 2013-12-25 | Nds Ltd | Obfuscated hardware multi-threading |
WO2013101031A1 (fr) * | 2011-12-29 | 2013-07-04 | Intel Corporation | Dissimulation de latence de défaut de cache d'instruction par exécution de consultations d'étiquette avant les accès aux instructions |
US9557999B2 (en) | 2012-06-15 | 2017-01-31 | Apple Inc. | Loop buffer learning |
US9753733B2 (en) * | 2012-06-15 | 2017-09-05 | Apple Inc. | Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer |
US9471322B2 (en) | 2014-02-12 | 2016-10-18 | Apple Inc. | Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold |
US10344615B2 (en) * | 2017-06-22 | 2019-07-09 | General Electric Company | Method and system for schedule predictive lead compensation |
GB2596872B (en) * | 2020-07-10 | 2022-12-14 | Graphcore Ltd | Handling injected instructions in a processor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63253433A (ja) * | 1987-04-10 | 1988-10-20 | Hitachi Ltd | 演算処理装置 |
US5163139A (en) * | 1990-08-29 | 1992-11-10 | Hitachi America, Ltd. | Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions |
US5404469A (en) * | 1992-02-25 | 1995-04-04 | Industrial Technology Research Institute | Multi-threaded microprocessor architecture utilizing static interleaving |
US5546593A (en) * | 1992-05-18 | 1996-08-13 | Matsushita Electric Industrial Co., Ltd. | Multistream instruction processor able to reduce interlocks by having a wait state for an instruction stream |
US5485629A (en) * | 1993-01-22 | 1996-01-16 | Intel Corporation | Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines |
DE69422780T2 (de) * | 1993-11-05 | 2000-08-17 | Intergraph Corp., Huntsville | Superskalare Rechnerarchitektur mit Softwarescheduling |
JP2987311B2 (ja) * | 1995-05-12 | 1999-12-06 | 松下電器産業株式会社 | プロセッサ及び翻訳装置 |
-
1997
- 1997-09-12 US US08/928,766 patent/US6076159A/en not_active Expired - Lifetime
-
1998
- 1998-09-04 IL IL13446098A patent/IL134460A0/xx unknown
- 1998-09-04 JP JP2000512135A patent/JP2001516918A/ja active Pending
- 1998-09-04 DE DE69821957T patent/DE69821957T2/de not_active Expired - Lifetime
- 1998-09-04 EP EP03029612A patent/EP1455271B1/fr not_active Expired - Lifetime
- 1998-09-04 KR KR1020007002605A patent/KR20010023914A/ko not_active Application Discontinuation
- 1998-09-04 EP EP03029611A patent/EP1406165B1/fr not_active Expired - Lifetime
- 1998-09-04 EP EP98944777A patent/EP1019806B9/fr not_active Expired - Lifetime
- 1998-09-04 WO PCT/US1998/018575 patent/WO1999014666A2/fr active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
JP2001516918A (ja) | 2001-10-02 |
WO1999014666A2 (fr) | 1999-03-25 |
DE69821957D1 (de) | 2004-04-01 |
EP1019806B9 (fr) | 2004-09-08 |
EP1455271A3 (fr) | 2005-03-09 |
US6076159A (en) | 2000-06-13 |
DE69821957T2 (de) | 2004-12-09 |
EP1455271A2 (fr) | 2004-09-08 |
EP1019806B1 (fr) | 2004-02-25 |
EP1406165A3 (fr) | 2004-12-01 |
WO1999014666A3 (fr) | 1999-07-29 |
EP1455271B1 (fr) | 2011-10-26 |
EP1019806A2 (fr) | 2000-07-19 |
EP1406165A2 (fr) | 2004-04-07 |
EP1406165B1 (fr) | 2012-03-21 |
KR20010023914A (ko) | 2001-03-26 |
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