DE69821957D1 - Datenprozessor mit paralleler decodierung und ausführung von daten- und adressbefehlen - Google Patents

Datenprozessor mit paralleler decodierung und ausführung von daten- und adressbefehlen

Info

Publication number
DE69821957D1
DE69821957D1 DE69821957T DE69821957T DE69821957D1 DE 69821957 D1 DE69821957 D1 DE 69821957D1 DE 69821957 T DE69821957 T DE 69821957T DE 69821957 T DE69821957 T DE 69821957T DE 69821957 D1 DE69821957 D1 DE 69821957D1
Authority
DE
Germany
Prior art keywords
data
execution
parallel decoding
address commands
data processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69821957T
Other languages
English (en)
Other versions
DE69821957T2 (de
Inventor
G Fleck
H Moller
Gigy Baror
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25456715&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69821957(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Publication of DE69821957D1 publication Critical patent/DE69821957D1/de
Application granted granted Critical
Publication of DE69821957T2 publication Critical patent/DE69821957T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G06F9/381—Loop buffering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G06F9/38585—Result writeback, i.e. updating the architectural state or memory with result invalidation, e.g. nullification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE69821957T 1997-09-12 1998-09-04 Datenprozessor mit paralleler decodierung und ausführung von daten- und adressbefehlen Expired - Lifetime DE69821957T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US928766 1986-11-10
US08/928,766 US6076159A (en) 1997-09-12 1997-09-12 Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline
PCT/US1998/018575 WO1999014666A2 (en) 1997-09-12 1998-09-04 Data processor with parallel decoding and execution of data and address instructions

Publications (2)

Publication Number Publication Date
DE69821957D1 true DE69821957D1 (de) 2004-04-01
DE69821957T2 DE69821957T2 (de) 2004-12-09

Family

ID=25456715

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69821957T Expired - Lifetime DE69821957T2 (de) 1997-09-12 1998-09-04 Datenprozessor mit paralleler decodierung und ausführung von daten- und adressbefehlen

Country Status (7)

Country Link
US (1) US6076159A (de)
EP (3) EP1019806B9 (de)
JP (1) JP2001516918A (de)
KR (1) KR20010023914A (de)
DE (1) DE69821957T2 (de)
IL (1) IL134460A0 (de)
WO (1) WO1999014666A2 (de)

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US7114056B2 (en) * 1998-12-03 2006-09-26 Sun Microsystems, Inc. Local and global register partitioning in a VLIW processor
US6615338B1 (en) * 1998-12-03 2003-09-02 Sun Microsystems, Inc. Clustered architecture in a VLIW processor
US6260133B1 (en) * 1999-02-08 2001-07-10 Kabushiki Kaisha Toshiba Processor having operating instruction which uses operation units in different pipelines simultaneously
US6237066B1 (en) * 1999-03-22 2001-05-22 Sun Microsystems, Inc. Supporting multiple outstanding requests to multiple targets in a pipelined memory system
EP1050808B1 (de) * 1999-05-03 2008-04-30 STMicroelectronics S.A. Befehlausgabe in einem Rechner
EP1050807A1 (de) * 1999-05-03 2000-11-08 Sgs Thomson Microelectronics Sa Speicherzugriff in einem Rechnerspeicher
EP1050809A1 (de) * 1999-05-03 2000-11-08 STMicroelectronics SA Befehlsabhängigkeit in einem Rechner
EP1050818A1 (de) * 1999-05-03 2000-11-08 STMicroelectronics SA Rechnerspeicherzugriff
US6393551B1 (en) * 1999-05-26 2002-05-21 Infineon Technologies North America Corp. Reducing instruction transactions in a microprocessor
US7302557B1 (en) * 1999-12-27 2007-11-27 Impact Technologies, Inc. Method and apparatus for modulo scheduled loop execution in a processor architecture
US6567895B2 (en) * 2000-05-31 2003-05-20 Texas Instruments Incorporated Loop cache memory and cache controller for pipelined microprocessors
US6748523B1 (en) * 2000-11-02 2004-06-08 Intel Corporation Hardware loops
US7472259B2 (en) * 2000-12-06 2008-12-30 Analog Devices, Inc. Multi-cycle instructions
US7069545B2 (en) * 2000-12-29 2006-06-27 Intel Corporation Quantization and compression for computation reuse
GB2381602B (en) 2001-10-12 2004-04-14 Siroyan Ltd Early resolving instructions
US6948162B2 (en) * 2002-01-09 2005-09-20 Sun Microsystems, Inc. Enhanced parallelism in trace scheduling by using renaming
US20030154363A1 (en) * 2002-02-11 2003-08-14 Soltis Donald C. Stacked register aliasing in data hazard detection to reduce circuit
KR100491323B1 (ko) * 2002-03-13 2005-05-24 (주) 네오시스트 독립 파이프라인에 의한 저장 방식을 갖는 전자 계산기
AU2003263491A1 (en) * 2002-10-11 2004-05-04 Koninklijke Philips Electronics N.V. Vliw processor with instruction address modification
US7159103B2 (en) * 2003-03-24 2007-01-02 Infineon Technologies Ag Zero-overhead loop operation in microprocessor having instruction buffer
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US7734901B2 (en) * 2005-10-31 2010-06-08 Mips Technologies, Inc. Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US7711934B2 (en) * 2005-10-31 2010-05-04 Mips Technologies, Inc. Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US7496771B2 (en) * 2005-11-15 2009-02-24 Mips Technologies, Inc. Processor accessing a scratch pad on-demand to reduce power consumption
US7873820B2 (en) * 2005-11-15 2011-01-18 Mips Technologies, Inc. Processor utilizing a loop buffer to reduce power consumption
US7562191B2 (en) * 2005-11-15 2009-07-14 Mips Technologies, Inc. Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme
KR100717055B1 (ko) 2005-11-18 2007-05-10 삼성전자주식회사 Ｃａｂａｃ 복호기에서 복수의 이진 값들을 파이프라인방식에 의하여 복호화하는 방법 및 이를 위한 복호화 장치
US20070204139A1 (en) 2006-02-28 2007-08-30 Mips Technologies, Inc. Compact linked-list-based multi-threaded instruction graduation buffer
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US20080016326A1 (en) 2006-07-14 2008-01-17 Mips Technologies, Inc. Latest producer tracking in an out-of-order processor, and applications thereof
US7370178B1 (en) 2006-07-14 2008-05-06 Mips Technologies, Inc. Method for latest producer tracking in an out-of-order processor, and applications thereof
US7681022B2 (en) * 2006-07-25 2010-03-16 Qualcomm Incorporated Efficient interrupt return address save mechanism
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US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US7594079B2 (en) * 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
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Also Published As

Publication number Publication date
US6076159A (en) 2000-06-13
KR20010023914A (ko) 2001-03-26
EP1455271A2 (de) 2004-09-08
EP1455271A3 (de) 2005-03-09
EP1019806B9 (de) 2004-09-08
WO1999014666A2 (en) 1999-03-25
EP1019806A2 (de) 2000-07-19
IL134460A0 (en) 2001-04-30
EP1406165A3 (de) 2004-12-01
EP1406165B1 (de) 2012-03-21
WO1999014666A3 (en) 1999-07-29
JP2001516918A (ja) 2001-10-02
EP1455271B1 (de) 2011-10-26
DE69821957T2 (de) 2004-12-09
EP1406165A2 (de) 2004-04-07
EP1019806B1 (de) 2004-02-25

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