IE903199A1 - Signal level converter - Google Patents

Signal level converter

Info

Publication number
IE903199A1
IE903199A1 IE319990A IE319990A IE903199A1 IE 903199 A1 IE903199 A1 IE 903199A1 IE 319990 A IE319990 A IE 319990A IE 319990 A IE319990 A IE 319990A IE 903199 A1 IE903199 A1 IE 903199A1
Authority
IE
Ireland
Prior art keywords
signal level
current source
current
supply voltage
cml
Prior art date
Application number
IE319990A
Other languages
English (en)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of IE903199A1 publication Critical patent/IE903199A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H03K19/017527—Interface arrangements using a combination of bipolar and field effect transistors [BIFET] with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
IE319990A 1989-09-04 1990-09-03 Signal level converter IE903199A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3929351A DE3929351C1 (US20030107996A1-20030612-P00015.png) 1989-09-04 1989-09-04

Publications (1)

Publication Number Publication Date
IE903199A1 true IE903199A1 (en) 1991-03-13

Family

ID=6388611

Family Applications (1)

Application Number Title Priority Date Filing Date
IE319990A IE903199A1 (en) 1989-09-04 1990-09-03 Signal level converter

Country Status (5)

Country Link
US (1) US5122689A (US20030107996A1-20030612-P00015.png)
EP (1) EP0416323A3 (US20030107996A1-20030612-P00015.png)
JP (1) JPH0399517A (US20030107996A1-20030612-P00015.png)
DE (1) DE3929351C1 (US20030107996A1-20030612-P00015.png)
IE (1) IE903199A1 (US20030107996A1-20030612-P00015.png)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW353535U (en) * 1990-11-19 1999-02-21 Hitachi Ltd Memory circuit improved in electrical characteristics
DE4112310A1 (de) * 1991-04-15 1992-10-22 Siemens Ag Signalpegelwandler
JPH06188718A (ja) * 1992-12-15 1994-07-08 Mitsubishi Electric Corp 半導体集積回路装置
US5343094A (en) * 1993-01-13 1994-08-30 National Semiconductor Corporation Low noise logic amplifier with nondifferential to differential conversion
JPH098637A (ja) * 1995-06-21 1997-01-10 Fujitsu Ltd 半導体装置
US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US7430171B2 (en) 1998-11-19 2008-09-30 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
DE60034131T2 (de) * 2000-12-04 2008-01-24 Infineon Technologies Ag Treiber für einen externen Feldeffekttransistor mit hoher Genauigkeit und Gate-Spannungsschutz
US7239636B2 (en) * 2001-07-23 2007-07-03 Broadcom Corporation Multiple virtual channels for use in network devices
US7295555B2 (en) * 2002-03-08 2007-11-13 Broadcom Corporation System and method for identifying upper layer protocol message boundaries
US7934021B2 (en) * 2002-08-29 2011-04-26 Broadcom Corporation System and method for network interfacing
US7346701B2 (en) 2002-08-30 2008-03-18 Broadcom Corporation System and method for TCP offload
US8180928B2 (en) * 2002-08-30 2012-05-15 Broadcom Corporation Method and system for supporting read operations with CRC for iSCSI and iSCSI chimney
US7313623B2 (en) * 2002-08-30 2007-12-25 Broadcom Corporation System and method for TCP/IP offload independent of bandwidth delay product
WO2004021626A2 (en) * 2002-08-30 2004-03-11 Broadcom Corporation System and method for handling out-of-order frames
US8995600B1 (en) * 2012-03-30 2015-03-31 Inphi Corporation CMOS interpolator for a serializer/deserializer communication application
US8824616B1 (en) * 2012-03-30 2014-09-02 Inphi Corporation CMOS interpolator for a serializer/deserializer communication application
US8885691B1 (en) 2013-02-22 2014-11-11 Inphi Corporation Voltage regulator for a serializer/deserializer communication application

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2443219B2 (de) * 1974-09-10 1976-09-23 Logikschaltung in komplementaer- kanal-mis-technik
DE3215518C1 (de) * 1982-04-26 1983-08-11 Siemens AG, 1000 Berlin und 8000 München Verknuepfungsglied mit einem Emitterfolger als Eingangsschaltung
JPS60141019A (ja) * 1983-12-28 1985-07-26 Nec Corp 論理回路
US4615951A (en) * 1984-12-18 1986-10-07 North American Philips Corporation Metallized rare earth garnet and metal seals to same
JPS62242419A (ja) * 1986-04-15 1987-10-23 Matsushita Electric Ind Co Ltd 化合物半導体集積回路
JP2585599B2 (ja) * 1987-06-05 1997-02-26 株式会社日立製作所 出力インタ−フエ−ス回路
JPH01195719A (ja) * 1988-01-30 1989-08-07 Nec Corp 半導体集積回路
JPH01261023A (ja) * 1988-04-12 1989-10-18 Hitachi Ltd 半導体集積回路装置
JP2580250B2 (ja) * 1988-05-11 1997-02-12 日本電信電話株式会社 バイポーラｃｍｏｓレベル変換回路

Also Published As

Publication number Publication date
US5122689A (en) 1992-06-16
DE3929351C1 (US20030107996A1-20030612-P00015.png) 1990-10-11
JPH0399517A (ja) 1991-04-24
EP0416323A3 (en) 1991-04-24
EP0416323A2 (de) 1991-03-13

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