IE891576A1

IE891576A1 - Electronic test systems

Info

Publication number: IE891576A1
Application number: IE157689A
Authority: IE
Inventors: William Gerard Fenton; Matthew Michael Collins; Francis Anthony Purcell
Original assignee: Revolverton Invest Ltd
Priority date: 1989-05-16
Filing date: 1989-05-16
Publication date: 1991-02-13
Also published as: GB9010928D0; IE80813B1; GB2233130A; IE891576L

Abstract

A test system for electronic apparatus including a microprocessor, has a control unit 1, a first communicating channel 4 for linking the control unit 1 to a command unit 2, which is preferably a computer, and a second communicating channel for linking the control unit 1 to electronic apparatus 3 to be tested. Control unit 1 is responsive to instructions received from command unit 2 to transmit in turn test instructions to apparatus 3 by way of the second communication channel. Control unit 1 also includes arrangements for receiving test results communicated from the apparatus 3, and retransmitting these test results to command unit 2. The second communication channel includes at least one probe 5a which has a region of random access memory and a multi-channel communication line.

Description

Electronic test systems This invention relates to test systems for electronic systems. In particular, the invention relates to a digital test system for functionally testing and trouble-shooting electronic systems or boards incorporating microprocessors in their circuitry.

According to the invention, there is provided a test system for electronic apparatus including a microprocessor, said test system comprising (a) control means, (b) first communicating means for communicating between the control means and a command means, and (c) second communicating means for communieating between the control means and a unit of electronic apparatus to be tested, the control means being responsive to instructions received from the command means to transmit test instructions to said unit of electronic apparatus, and the control means also including means for receiving test results communicated by said unit of electronic apparatus and transmitting said test results to the command means. - 2 Said second communicating means preferably includes a first probe having a region of random access memory and a multi-channel communication line. In a favoured embodiment, the second communication means may also include, as required by the unit of electronic apparatus under test, between one and three further probes, each of which has a region of random access memory.

The control means suitably includes processing means for receiving information from said command means and for retransmitting said information in appropriate form to the unit of electronic apparatus under test for activating the microprocessor of said unit of apparatus to perform a desired operation or sequence of operations. Said first probe then suitably includes means for enabling transfer of the results of a said desired operation or sequence of operations from said unit of apparatus under test to said control means for onward retransmission to the command means.

The control means of the system of the invention preferably consists of a unit including a power supply and a main circuit board on which a number of operating regions are defined, these including, inter alia, a central processor unit region and a read only memory emulation area. This latter, in conjunction with said first probe and also in conjunction with one or more of said further probes, as required, enables emulation by the system of the invention of read only memory chips of the unit of apparatus under test. The command means most suitably consists of a computer, such as a personal computer, and test instructions are transmitted in the form of electronic data from the computer to the control unit of the system during a test operation, for processing as required to provide test instructions appropriate to a particular unit of apparatus to be tested. The probes of the system of the invention preferably consist of individual entities connected between the control unit of the system and read only memory chip sockets of the unit of apparatus to be tested.

The control unit board may also include a logic probe area for co-operation with probe means for placement at individual pins of the circuitry of a unit of apparatus to be tested, to communicate between one or more said pins and the control unit of the system and enable display of test results for any pin location by the command means. A clock probe may also be associated with said probe means.

The control unit most suitably also includes a self-test board, for checking the proper functioning of the test system itself, as required.

The command means is suitably loaded with test instructions as software, and a particular test routine or routines then selected by the user, suitably by means of a menu display. The selected test instructions are adapted to the particular microprocessor used by the unit of apparatus to be tested and are inputted to the unit to be tested by the control unit and probes of the system of the invention. Test results communicated by the unit tested are retransmitted to the command means by way of the probe(s) and control unit for screen display and user review and consideration as required.

The invention also provides a method of testing electronic apparatus including a microprocessor, the method comprising communicating instructions from a command means to a control means of a test system, the control means being responsive to said instructions to retransmit same to the unit to be tested, and the control means being also responsive to test results communicated from said unit to be tested for retransmission to said command means for user monitoring and review.

An embodiment of the invention will now be described having regard to the accompanying drawings, in which: Figure 1 is a schematic overall representation of a system in accordance with the invention, Figure 2 is a schematic representation of the control unit of the system of Figure 1, Figure 3 is a schematic representation of the functioning of a ROM probe in the system of Figure 1, Figure 4 is a diagranmatic representation of the sequence of transmission of communication signals or handshaking during the transmission of information to and from a unit under test via a ROM probe of the system of Figure 1, and - 4 Figure 5 provides a further diagrammatic representation of the communications link between the control unit of the test system and a unit under test.

As shown in Figure 1, a system in accordance with the invention provides a control unit 1 for interposition between a personal computer 2 and a unit under test (UUT) 3. The connection 4 between the personal computer 2 and the control unit 1 of the system of the invention takes place by way of a standard RS232C cable. The test system also includes a number of test pods intended to meet various test requirements. These pods include between one and four ROM probes 5a, 5b ... etc., the number used depending on the size of the microprocessor in the unit under test 3. Each ROM probe 5a, 5b ... etc. is connected between the control unit 1 and the unit under test 3, the connection to the latter taking place via ROM chip sockets 6 on the unit under test. In addition to the ROM probes, a clock probe 7 and a logic probe 8 may also be interconnected between control unit 1 and the unit under test 3. The control unit 1 also includes a self-test board 9, provided to ensure proper operation of the other test pods.

Referring now to Figure 2, the control unit 1 houses a power supply 11 and a main board 10 on which a number of separate logic areas are defined. The areas in question are a central processor unit (CPU) area 12, a ROM emulation area 13, also referred to as a so-called romulation region or area, and a logic probe area 14. Also represented in Figure 2 is the self-test area or board 9. The RS232 interface 4 to the personal computer extends from main board 10. The control unit thus consists of the power supply unit 11 plus the main board 10 containing the CPU area 12, the romulation area 13, the logic probe area 14 and the self-test area 9. Up to four ROM probes 5a, 5b ... etc. are provided, along with the clock probe 7, a single logic probe 8, and a reset probe. Main board 10 of control unit 1 is connected to probes 5a, 5b, 5c and 5d by respective links designated 15a, 15b, 15c and 15d, while the connections between board 10 and clock 7, logic probe 8 and the reset probe are indicated by references 16, 17 and 18 respectively. Further optional features include a logic monitor and an in-circuit tester.

The central processing unit or CPU 12 of Figure 2 contains the control circuitry for the entire test system. This includes the following: - 5 Z80 microprocessor running at 6 MHz, K battery backed-up static random access memory, K read only memory, RS232C serial port, timer control circuitry, and interface circuitry for cooperation with the personal computer 2.

Thus the test system is itself microprocessor based and, when used in conjunction with a personal computer 2, the system of the invention may be configured to test microprocessor systems varying in size from 8 bit up to 32 bit.

Having identified the component parts of the system, its operation can now be briefly described as follows, with further subsequent enlargement on individual steps in the test procedure. The system is set up in the arrangement shown in Figure 1 between the personal computer 2 and the unit under test 3. Appropriate test probes 5a, 5b ... etc., 7, and 8 are connected between the control unit 1 and the unit under test 3. Software for the particular test routines to be carried out is then downloaded from the personal computer 2 to the control unit 1. This software is in turn further downloaded onto the unit under test 3 by way of the ROM probes 5a, 5b ... etc., which replace the onboard ROM chips of the unit under test for the purposes of carrying out test operations. The software downloaded from the personal computer is arranged to appear to the microprocessor of the unit under test as ROM, i.e. read only memory, and to cause this microprocessor to perform certain functional tests on its address/data buses, its RAM areas, its I/O (input/output) areas, and so on. A main probe 5a of the ROM probes 5a, 5b ... etc. contains a communication channel through which the test control unit 1 informs the microprocessor of the unit under test as to which tests are to be performed. The same communication channel also allows the unit under test to transfer or disclose the result of each test to the control unit.

The control unit 1 in turn relays the result to the user by way of the screen of the personal computer 2.

The feature of ROM emulation, hereinafter referred to as romulation, is an important and central technique of the testing process employed in the system of the invention. On the main board 10, the romulation area 13 is a region of logic which interfaces with the ROM probes 5a, 5b ... etc.

Depending on the size of the microprocessor of the unit under test, between one and four ROM probes are used. For the purposes of carrying out test routines, these ROM probes replace the ROM chips of the unit under test.

Figure 3(a) is a diagrammatic representation of ROM probe 5a, which can be regarded as comprising a buffer 20 connected between the control unit 1 and RAM 19, i.e. random access memory, of the probe itself, with a further buffer 21 interposed between the RAM block 19 and the unit under test 3.

When the personal computer 2 has downloaded the appropriate test software to the CPU area 12 of the control unit 1, it is then passed on to the romulation area 13 of main board 10. The test software is then further transferred to the RAM 19 of the ROM probe 5a by enabling the first buffer 20, i.e. that between the control unit and the RAM block 19 of the ROM probe. Further onward transfer of the software test routines to the unit under test is then achieved by enabling the second buffer 21.

The software in question is in the code of the microprocessor of the unit under test and is configured to cause the microprocessor to stimulate the address/data buses of the unit under test and in so doing, to functionally test the unit under test. Each ROM probe 5a, 5b ... etc. provides 8 K of memory space. As this feature of the test system replaces the ROM chips of the unit under test, the process is therefore referred to as romulation.

The first or main ROM probe 5a covers bits zero to seven of the microprocessor address bus and also contains a communication channel between the test unit 1 and the unit under test 3, for the transfer of information in each direction between these two units. This communication line is designated by reference 23 in the central part of Figure 3, i.e. Figure 3(b). Two handshaking lines 24 and 25, indicated in the lowermost part of Figure 3, i.e. Figure 3(c), are also provided to control data transfer.

In use of the system of the invention, the user selects a test to be carried out by the system of the invention. This selection is carried out on the personal computer 2. The control unit 1 then passes appropriate information for the test in question, in binary format, to the unit under test 3 via the eight bit communication channel 23. This channel corresponds to address AO1H in ROM. The data transmitted normally consists of one byte to describe the test, along with a number of other bytes defining the address range or a data pattern to be used by the test. If, for example, the data pattern is 2220002FFF, this may describe a RAM read/write ability check on the range 2000 to 2FFF of the RAM of the unit under test.

In order to transfer a single byte, the data ready handshaking line 24 of the control unit goes low and places the byte on the communication channel 23. This change is indicated in the uppermost portion of Figure 4. When the unit under test sees its data ready line pulled low, i.e. at the unit under test end of the handshaking line 24, it reads A01H, where the actual data is perceived, and then pulls its own data acknowledge line low. These further steps are indicated in the second and third rows or lines of Figure 4. The control unit 1 then sees its data acknowledge line go low, by receipt of an appropriate signal along handshaking line 25, this change reporting to the control unit that the data transmitted by it has been received by the unit under test. The control unit 1 may then proceed to transmit another byte in exactly the same manner. The timing considerations in question will be clear from Figure 4.

The foregoing process is appropriate to the transmission of instructions from the control unit to the unit under test, in other words, to the situation where the control unit is informing the unit under test of what to do, but, in order to carry out test procedures, the unit under test must also communicate the results of tests back to the control unit. However, read only memory chips cannot write data to any location. The problem of arranging for the unit under test to coimnunicate the results of the various tests carried out back to the control unit, using the ROM probes, is overcome in the romulation process provided by the present invention.

The conmunications channel of the invention is further enlarged upon in Figure 5. On the control unit side of the coiranunications channel, standard ports 31 to 34 are provided, connected to the Z80 microprocessor in the control unit. The invention allows the read and write input/output ports 35 to 38 on the unit under test (UUT) side of the invention to be accessed via read only memory, thereby enabling bidirectional communications through a ROM device. The ROM probe has an 8K address space, and 512 bytes of this are reserved for the communications channel, area 900-AFFH.

Ports 35 and 38 of the unit under test may be accessed with relative facility, as both are read devices. Thus a simple read instruction from the unit under test casuses the contents to be placed on the UUT address bus 41 for examination via memory decoder 42.

In order to access ports 36 and 37, different techniques are required. At port 37, a J-K flip-flop with preset and clear inputs is provided. The queue output is fed to port 33 on the control unit side.

Memory decode signals A08 and AOC are connected to the preset and clear inputs of the flip-flop. Thus reading memory A08 sets the output of port 37, and reading address AOC clears this output.

At port 36, the lower eight address lines of the UUT are latched, when addresses 900-9FF are read. Thus when 9xx is read, xx is latched.

When 978 is read, port 36 will output 78.

In order to transfer bytes, the following procedure is therefore followed: Control unit to UUT transfer: Control unit UUTWrite byte to P#1 Write zero to P#4 Read UUT#1 Clear UUT#3 by reading AOC Write one to P#4 Set UUT#3 by reading A08 UUT to Control unit transfer: Control unit UUTWrite byte xx to UUT#2 by reading 9xx.

Clear UUT#3 by reading AOC Read P#2 Write zero to P#4 Set UUT#3 by reading A08 Write one to P#4 The main ROM probe 5a thus has only 7.5 K of memory space available to the microprocessor of the unit under test. The other half byte is used to effect the communication process. The decoder on the probe waits for the microprocessor of the unit under test to read a value in the specific range of ROM available. If, for example, the total range of ROM is 0 to ZFFFH, then the decoder waits for values in a range of Y00 to YFF. If such a read occurs, then the output of the decoder is used to enable the flip-flop, which then causes the low byte of the address bus of the unit under test to be latched onto the communication channel. In addition, the microprocessor of the unit under test reads ROM location A02H, which acts as a toggle to pull the data ready line 24 low. The control unit now sees its own data ready line go low, and accordingly reads the eight bit communication channel 23 and pulls its data acknowledge line low. The microprocessor of the unit under test looks at its own data acknowledge line by reading ROM location AOOH.

It then knows that one byte has been successfully transferred and can proceed to transmit another byte, if necessary. Since this process occurs when any ROM address in the range Y00 to YFF is read, then any eight bit combination can be transmitted to the control unit of the system of the invention. In simple terms, what is achieved by the system of the invention is that in reading a location in read only memory, a write operation has also been brought about.

The complete range of test sequences provided by the system of the invention are all implemented by means of software. The software is provided in diskette format accompanying the system. The romulation code, as installed in the ROM probes, is in the language of the microprocessor of the unit under test. This amounts to 8 K of memory per ROM probe, except for the first or main ROM probe 5a, which has only 7.5 K. In these memory areas, the assembly language routines necessary for carrying out functional tests for the unit under test, such as bus checks, RAM read/write ability, wrong signature checks, I/O read/write ability, and so on are contained.

The selection of each or any of these tests is achieved by means of the personal computer 2. The range of test options is presented to the user in menu format on the screen of the computer. The user employs the keyboard to select a particular test, and the computer system is then activated to inform the control unit 1 of the system of the invention as to which test is to be attempted. Instructions from the computer to the control unit are transferred by means of a high level computer language. The control unit 1 then passes this information forward to the microprocessor of the unit under test by means of the communication channel 23 of the main ROM probe 5a. The data transferred is in the form of a number of bytes of information. - 10 In the discussion of romulation, the example of a data pattern of 2220002FFF was quoted. The first byte of this data, 22, represents an indication to the romulation code, i.e. the code in the ROM probe, to run a RAM test. The next two bytes, 2000, are then identified by this sub-routine as the required start address for the test. The last two bytes, 2FFF, identify the end address of the test.

The actual test routine is also a number of bytes in length. For this example, it consists of a number of read and write statements to each location in the address range. After each read or write cycle, the processor decides whether or not the test is proceeding properly. If an error has occurred, execution jumps to an error handling routine to inform the operator of the location and nature of the error. This information, in binary format, is transmitted back to the control unit 1 by way of the communication channel 23 of the main ROM probe 5a. The control unit 1 then relays this message to the computer 2, for conversion to an on-screen message displayed to the user.

Different software is loaded into the ROM probes for testing different types of microprocessor. This lends the system a high degree of versatility, as no additional hardware is required. As long as the correct software is contained in the probes, the system is ready to test all boards containing the type of microprocessor in question.

The further features of the invention indicated on Figure 1 will now be described in more detail. Logic probe 8 consists of a hand-held device used for trouble-shooting single lines of component pins on the unit under test and for examining signals present at such locations. The tip of the probe may be placed anywhere on the unit under test. A switch on the probe allows the signal at the probe to be sampled and saved to a memory storage area using the control unit 1. 1,024 samples are taken at any one location. The sampling rate may be specified in one of two ways. The rate may be selected from a number of rates supplied by the control unit itself, ranging from 10 nseconds up to 1 msecond, or, by use of the clock probe 7, an external clock may be used to specify the sampling rate. Two further signals may also optionally be employed by the logic probe, these being a clock qualifier level and a trigger level. Neither is however essential.

When the probe is switched on, the first eight samples taken are filed into eight toggle flip-flops. The outputs of these eight flip-flops are simultaneously inputted to an eight bit latch. The next eight samples are then filed into the eight flip-flops, and at the same time, the latched eight bits are placed into one byte of RAM. This method is used to ensure that when the fastest sampling rates are selected, i.e. of the order of nanoseconds, individual samples are latched into RAM. At very high rates of sampling, RAM may not itself be able to latch individual samples with sufficient speed. Following saving of the 1,024 samples in RAM, eight at a time, these are then available for display on the screen of the personal computer for analysis by the operator.

The self-test feature 9 of the invention will now also be briefly described. The self-test board enables operation of the probes themselves to be checked. The probe sockets 6 which are normally inserted into the unit under test are plugged into the self-test board 9. The logic circuits on the main board 10 of the control unit 1 then examine the operation of each probe and ensure that they are working properly. The provision of this facility enables the operator to be certain that any errors apparently located on the the unit under test are truly resident in that unit and are not caused by faulty test equipment.

A number of further expansion slots are also provided on the control unit, to allow, for example, the installation of a logic monitor unit. This unit allows up to eight individual lines to be sampled simultaneously in a similar manner to the single line sampling technique permitted by the logic probe 8.

A further feature optionally incorporated in the system of the invention is an in-circuit tester. This unit expands the scope of the capabilities of the system of the invention by allowing it to examine the cause of individual component failures in a unit under test, while these components remain in situ on the board. Thus the in-circuit tester allows component failure analysis without requiring removal of the component for this purpose.

Claims

1. A test system for electronic apparatus including a microprocessor, said test system comprising (a) (b) (c) control means, first communicating means for communicating between the control means and a command means, and second communicating means for communicating between the control means and a unit of electronic apparatus to be tested, the control means being responsive to instructions received from the command means to transmit test instructions to said unit of electronic apparatus, and the control means also including means for receiving test results communicated by said unit of electronic apparatus and transmitting said test results to the command means.

2. A test system according to Claim 1,wherein said second communicating means includes a first probe having a region of random access memory and a multi-channel communication line.

3. A test system according to Claim 2, wherein said second communicating means also includes between one and three further probes, each of which has a region of random access memory.

4. A test system according to Claim 3, wherein said control means includes processing means for receiving information from said command means and for retransmitting said information in appropriate form to the unit of electronic apparatus under test for activating the microprocessor of said unit of apparatus to perform a desired operation or sequence of operations.

5. A test system according to Claim 4, wherein said first probe includes means for enabling transfer of the results of a said desired operation or sequence of operations from said unit of apparatus under test to said control means for onward retransmission to the command means.

6. A test system according to Claim 5, wherein the control means consists 13 of a unit including a power supply and a main circuit board on which a number of operating regions are defined, these including a central processor unit region and a read only memory emulation area.

7. A test system according to Claim 6, wherein said command means consists of a computer for transmission of test instructions in the form of electronic data from the computer to the control unit of the system during a test operation, for processing as required to provide test instructions appropriate to a particular unit of apparatus to be tested.

8. A test system according to Claim 7, wherein the probes of the system of the invention consist of individual entities connected between the control unit of the system and read only memory chip sockets of the unit of apparatus to be tested.

9. A test system according to Claim 8, wherein the control unit board also includes a logic probe area for co-operation with probe means for placement at individual pins of the circuitry of a unit of apparatus to be tested, to communicate between one or more said pins and the control unit of the system and enable display of test results for any pin location by the command means.

10. A method of testing electronic apparatus including a microprocessor, the method comprising communicating instructions from a command means to a control means of a test system, the control means being responsive to said instructions to retransmit same to the unit to be tested, and the control means being also responsive to test results coranunicated from said unit to be tested for retransmission to said command means for user monitoring and review.

11. A method of testing electronic apparatus including a microprocessor, substantially as described herein with reference to the accompanying drawings.

12. A test system for electronic apparatus including a microprocessor, substantially as described herein with reference to and as shown in Figures 1 to 5 of the accompanying drawings.