IE43560B1 - Hall effect device - Google Patents

Hall effect device

Info

Publication number
IE43560B1
IE43560B1 IE2361/76A IE236176A IE43560B1 IE 43560 B1 IE43560 B1 IE 43560B1 IE 2361/76 A IE2361/76 A IE 2361/76A IE 236176 A IE236176 A IE 236176A IE 43560 B1 IE43560 B1 IE 43560B1
Authority
IE
Ireland
Prior art keywords
layer
resistivity
type
substrate
hall effect
Prior art date
Application number
IE2361/76A
Other versions
IE43560L (en
Original Assignee
Itt
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Itt filed Critical Itt
Publication of IE43560L publication Critical patent/IE43560L/en
Publication of IE43560B1 publication Critical patent/IE43560B1/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00Hall-effect devices
    • H10N52/101Semiconductor Hall-effect devices

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  • Hall/Mr Elements (AREA)

Abstract

1518957 Hall effect devices STANDARD TELEPHONES & CABLES Ltd 25 Nov 1975 48355/75 Heading H1K A Hall effect device comprises an n-type epitaxial Si layer 1 on a p-type Si substrate 2, the resistivity of the substrate 2 being at least 4 #cm. and at least four times that of the epitaxial layer 1. Silica layers 3 are situated on opposed major surfaces, and ohmic contacts 4 are made to the layer 1 through diffused n+ region 5. The doner dopant in layer 1 is chosen to have a low diffusion coefficient so that it does not significantly penetrate the substrate 2 during growth of the layer 1.

Description

This invention relates, to Hall effect devices;.
Hall effect devices having a high output voltage are troubled by two major difficulties, (a) the temperature coefficient and (b) the offset voltage, i.e, the difference in voltages, which should be equal, at the Hall output contacts when a sampling current is being passed between the input contacts under zero magnetic field. If an offset voltage is present i't usually has to be compensated for using a balancing resistor in the external circuitry. This can be a costly and time consuming exercise.
An object of the invention ts to obtain high output voltage with low offset voltages, together with low temperature sensitivity.
According to the invention there is provided a Hall effect device comprising an n-type epitaxially grown relatively low resistivity layer on one major surface of a relatively high resistivity p-type silicon suhstrate, silica passivation layers one on each major surface of the device, and first and second sets of ohmic contacts formed by diffusion of n+ regions- in the epitaxial layer via windows formed in the silica layer on the epitaxial layer, in which the n-type dopant of the epitaxial layer has a low diffusion coefficient in silicon therehy inhibiting substantially diffusion across thep-n interface during the epitaxial growth process, and in which the resistivity of the substrate is at least 4 ohm cm. and is at least four times that of the resistivity of the epitaxial layer.
An embodiment of the invention will now be described with reference to the accompanying drawings, in which:-24 3 5 6 0 Figs, 1 and 2 are plan and sectioned side views respectively of a Hall effect device and Figs. 3 and 4 are plan views or modified forms of the device.
The Hall effect device shown in Figs. 1 and 2 is rectangular in shape, typically measuring lmmx2mm, and comprises an epitaxially grown layer 1 of n-type silicon, of resistivity 1,0 ohm cm and thickness 20jua,on a high resistivity (10 ohm cm) p-type silicon substrate 2.
There are Si02 passivating layers 3 on both major surfaces of the device. There are no side passivating layers as the device is produced b,y standard silicon wafer processes commencing with a wafer from which individual devices are diced.
Edge located, strip-shaped, ohmic output contacts 4, e.g. of Al of width 0.25mm and length 0.30mm, are provided by first diffusing into the n-type layer 1 n+ regions 5 to a depth of approximately 2pm via suitable windows in the SiO2 layer 3, followed by Al deposition. Edge located, strip-shaped, ohmic input contacts 6 are provided in like manner.
The n-type dopant is selected to have a low diffusion coefficient in silicon, to inhibit diffusion across the p-n interface during the epitaxial growth process, as the thickness of the layer 2, i.e. of the Hall plate, is an important parameter. Suitable dopants are phosphorus, arsenic or antimopy; For the p-type substrate 1, a suitable dopant is boron.
A selection of the resistivity of the n-type layer in the range 0.1 to 2 ohm cm, with a substrate resistivity at least four times that of the n-type layer, the substrate having a resistivity of at least 4 ohm cm., provides a Hall effect device giving high output with low offset voltage, i.e. *£10% of the output voltage for a 20mA sampling current and a magnetic field of IkG, the device having a very low temperature sensitivity, i.e. -<5% variation from 0°-125°C.
Utilisation of the epitaxial process permits the carrier concentration and resistivity to be controlled within +10%, and the thickness of the n-type layer can be controlled within +5%. Thus the total error in the output is +15%. In other technologies, cutting samples off a slice at random, the total error will be nearer + 30%, -34 3 5 0 0 A further advantage of the silicon epitaxial approach is that any shape can be defined in the n-type layer by a final isolation diffusion, e.g. a cross shape isolation diffusion 7a as shown in Fig. 3, or a clover leaf shaped isolation voltage, diffusion 7b as shown in Fig. 4. Both these shapes give an improved Hall output' and reduced offset.voltages.

Claims (6)

1. A Hall effect device comprising an n-type epitaxially grown relatively Ipw resistivity layer on one major surface of a relatively high resistivity p-type silicon substrate, silica passivation layers one on each major surface of the device and first and second sets of ohmic contacts formed by diffusion of n + regions in 5 the epitaxial layer via windows formed in the silica layer on the epitaxial layer, in which the n-type dopant of the epitaxial layer has a low diffusion coefficient in silicon thereby inhibiting substantially diffusion across the ρ-n interface during the epitaxial growth process, and in which the resistivity of the substrate is at least 4 ohm cm. and is at least four times that of the resistivity of the 10 epitaxial layer.
2. A device as claimed in claim 1 or 2. in which the resistivity of the epitaxial layer is in the range 0.1 to 2 ohm cm.
3. A device as claimed in claim 1 or 2, in which the n-type dopant is phosphorus arsenic or antimony. 15
4. A device as claimed in claims 1, 2 or 3, in which the o-type dopant of the substrate is boron.
5. A device as claimed in any one of claims 1 to 4, in which the effective shape of the device is defined by an isolation diffusion in the n-type layer.
6. A Hall effect device substantially as described and as shown in Figs. 1 and 20 2, or in Fig. 3, or in Fig. 4 of the accompanying drawings.
IE2361/76A 1975-11-25 1976-10-26 Hall effect device IE43560B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB48355/75A GB1518957A (en) 1975-11-25 1975-11-25 Hall effect device

Publications (2)

Publication Number Publication Date
IE43560L IE43560L (en) 1977-05-25
IE43560B1 true IE43560B1 (en) 1981-03-25

Family

ID=10448322

Family Applications (1)

Application Number Title Priority Date Filing Date
IE2361/76A IE43560B1 (en) 1975-11-25 1976-10-26 Hall effect device

Country Status (9)

Country Link
AU (1) AU1986176A (en)
CH (1) CH601919A5 (en)
DE (1) DE2652322A1 (en)
ES (1) ES453598A1 (en)
FR (1) FR2333354A1 (en)
GB (1) GB1518957A (en)
IE (1) IE43560B1 (en)
NL (1) NL7613064A (en)
ZA (1) ZA766083B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19857275A1 (en) * 1998-12-11 2000-06-15 Johannes V Kluge Integrated split-current Hall effect magnetic flux density sensor, e.g. for automobile and automation applications, has magnetic field sensitive elements and contacts produced by one or two photolithographic masking steps
DE19908473B4 (en) 1999-02-26 2004-01-22 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Hall sensor with reduced offset signal

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL158658B (en) * 1967-09-08 1978-11-15 Philips Nv HALL ELEMENT AND COLLECTORLESS ELECTRIC MOTOR IN WHICH THIS HALL ELEMENT IS APPLIED.

Also Published As

Publication number Publication date
DE2652322A1 (en) 1977-06-02
GB1518957A (en) 1978-07-26
ES453598A1 (en) 1977-12-16
NL7613064A (en) 1977-05-27
IE43560L (en) 1977-05-25
FR2333354A1 (en) 1977-06-24
AU1986176A (en) 1978-06-01
CH601919A5 (en) 1978-07-14
ZA766083B (en) 1977-10-26

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