IE20030544A1 - A private branch exchange, and a method for selectively communicating a central processing unit with respective modules connected to the private branch exchange - Google Patents

Abstract

A PBX (1) comprises a central processing unit (2) for controlling the PBX (1). A plurality of modules (6) for facilitating expansion of the PBX (1) at respective selectively addressable primary locations (4) through plus and socket connectors (7,5) and communicate with the central processing unit (2) through a primary bus (8) using SPI communication protocol. Primary address registers (14) at the respective primary locations (4) store a primary address code of each primary location which identifies the module (6) connected at that primary location (4). A plurality of secondary locations (15) in each module (6) are addressable through a programmable logic device (17) by the central processing unit (2). A comparator (19) compares a primary address on chip select lines (13) of the primary bus (8) with the stored primary address code in the primary address register (14) for determining if the module (6) is being addressed. A read/write circuit (20) reads the first byte of data of the communication after selection of a module (6) for determining the secondary location 915) which is to be addressed by the central processing unit (2). A main switch circuit (23) switches the selected secondary location (15) to the central processing (2), and a switch (27) switches a chip enable line (12) of the primary bus (8) to the main switch circuit (23) for switching to the selected secondary location (15). <Figures 1 & 2>

Description

A private branch exchange, and a method for selectively communicating a central processing unit with respective modules connected to the private branch exchange” The present invention relates to a private branch exchange (PBX), and in particular to a PBX comprising a central processing unit and a plurality of primary locations for receiving plug-in modules whereby the central processing unit is selectively communicatable with the plug-in modules. The invention also relates to a method for selectively communicating a central processing unit with the respective modules in the PBX.

PBXs may be supplied in modular form. For example, a primary module may be provided with a switching circuit for switching a plurality of extension lines to each other, and for switching the extension lines to exchange lines. In general, a central processing unit is provided for controlling the switching circuit. Such a primary module may have a limited capacity, for example, it may have a capacity for switching only eight extension lines and two exchange lines. By providing a plurality of secondary modules which can be readily plugged into the primary module, the capacity of the primary module can be expanded to increase the extension line and exchange line switching capacity of the PBX. For example, one such secondary module may have a capacity for switching additional extension lines, and another module may have a capacity for switching additional exchange lines, and so on. As additional secondary modules are plugged into the primary module, the capacity of the PBX is progressively expanded.

Such PBXs have many advantages. For example, they facilitate small growing firms. A small firm may initially purchase a primary module, and as the firm expands additional secondary modules may be plugged into the primary module for progressively increasing the capacity of the PBX. Another and particularly important advantage of such PBXs is that they facilitate a manufacturer in minimising its inventory of PBXs. For example, instead of having to hold a large range of PBXs in stock with different extension and exchange line switching capacities, a manufacturer need only retain an appropriate number of primary modules and fM secondary modules, and from the inventory of primary and secondary modules can then supply a wide range of PBX capacities by merely assembling the appropriate number of secondary modules to a primary module prior to supplying a PBX. In this way the manufacturer with minimum inventory has the ability to supply a wide range of PBXs with different switching capacities.

However, a problem with such modularised PBXs is that in many cases it is difficult to identify the module or modules which have been plugged into the various module receiving locations, and this can lead to significant problems both at the assembly stage, and indeed, during use of the PBX.

There is therefore a need for a PBX which overcomes this problem, and there is also a need for a method for selectively communicating a central processing unit of a PBX with respective modules in the PBX.

The present invention is directed towards providing such a PBX and such a method for selectively communicating a central processing unit with respective modules of a PBX.

According to the invention, there is provided a PBX comprising a central processing unit, a plurality of selectively addressable primary locations for receiving respective plug-in modules, a connecting means provided at each primary location for receiving one of the plug-in modules, a primary bus interconnecting the central processing unit with the primary locations for communicating the central processing unit with each module plugged into a corresponding one of the primary locations, the primary bus comprising at least two chip select lines for carrying primary address codes of the respective primary locations for selecting the modules plugged into the respective primary locations, a chip enable line for carrying a chip enable signal for initiating communication between the central processing unit and the selected module, and at least one serial data communication line for communicating data between the central processing unit and the selected module in a desired communication protocol, at least one plug-in module being plugged into the connecting means at one of the primary locations, each module comprising a plurality of selectively addressable secondary locations, a programmable logic device comprising a comparing means for comparing primary address codes on the primary bus with the primary address code ofthe corresponding primary location, a reading means responsive to the comparing means determining that a primary address code compares with the primary address code ofthe corresponding primary location, for reading a secondary address code at a predetermined location in a data signal on the primary bus for identifying one of the secondary locations of the module with which data is to be communicated with the central processing unit, a main switch means responsive to the programmable logic device for coupling the selected one of the secondary locations with the central processing unit through the at least one serial data communication line of the primary bus, and a secondary switch means responsive to the programmable logic device for coupling the selected one of the secondary locations with the chip enable line of the primary bus.

In one embodiment of the invention the secondary switch means is responsive to the primary address code remaining on the chip select lines of the primary bus for retaining the selected one of the secondary locations coupled to the chip enable line of the primary bus.

In another embodiment of the invention the primary bus comprises three chip select lines for accommodating seven primary address codes. Preferably, each secondary address code is a three bit code. Advantageously, the predetermined location of the data signal at which each secondary address code is located comprises the first byte of the data signal. Ideally, each secondary address code is provided by the three least significant bits ofthe data signal.

In one embodiment of the invention each secondary location is connected to the programmable logic device by a secondary bus.

Preferably, each secondary bus comprises one line which is coupled to the secondary switch means.

In one embodiment of the invention the lines of each secondary bus are coupled to IE OS 05 4 4 the main switch means.

In one embodiment of the invention each primary location comprises a primary address register for storing the primary address code of the corresponding primary location. Advantageously, the comparing means of each module reads the primary address code of the primary location to which the module is plugged in from the corresponding primary address register through the connecting means.

Additionally the invention provides a method for selectively communicating between a central processing unit of a PBX and a plurality of plug-in modules plugged into corresponding selectively addressable primary locations of the PBX, wherein each module comprises a plurality of selectively addressable secondary locations, the method comprising the steps of providing a primary bus interconnecting the central processing unit with the primary locations, the primary bus comprising at least two chip select lines for carrying primary address codes of the respective primary locations for selecting the modules plugged into the respective primary locations, a chip enable line for carrying a chip enable signal for enabling a selected one of the secondary locations for initiating communication between the central processing unit and the selected secondary location, and at least one serial data communication line for communicating data between the central processing unit and the selected modules in a desired communication protocol, the method comprising the further steps of operating each module plugged into a primary location for comparing primary address codes on the chip select lines of the primary bus with the primary address code of the corresponding primary location for determining if the module plugged into the primary location is being addressed, operating an addressed module for reading a secondary address at a predetermined location in a data signal on the primary bus for identifying the secondary location of the addressed module with which data is to be communicated with the central processing unit, and switching the selected secondary location to the at least one serial data communication line of the primary bus, and separately switching the selected secondary location to the chip enable line of the primary bus for providing a chip enable signal to the secondary location for indicating the commencement of data transfer. 4 4 In one embodiment of the invention the selected secondary location is switched to the chip enable line for so long as the primary address code of the primary location to which the module is connected remains on the chip select lines.

The invention will be more clearly understood from the following description of a preferred embodiment thereof, which is given by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a block representation of a PBX according to the invention, and Fig. 2 is a circuit diagram of a module of the PBX of Fig. 1 illustrated connected into the PBX.

Referring to the drawings, there is illustrated a PBX according to the invention indicated generally by the reference numeral 1. The PBX comprises a central processing unit 2 which controls the operation of the PBX 1 as well as a switching circuit (not shown) for setting up connections between respective extension lines (not shown), and between the respective extension lines (not shown) and exchange lines (also not shown). The switching circuits of such PBXs will be well known to those skilled in the art, and it is not intended to describe the switching circuit or the actual functioning of this aspect of the PBX 1 for switching calls between extension lines and between extension and exchange lines. The PBX 1 comprises a plurality of primary locations 4, only three of which are illustrated in Fig. 1.

Each primary location 4 comprises a connecting means provided by a multiple contact socket connector 5 for selectively and releasably receiving modules 6 for expanding the extension and exchange line switching capacity of the PBX 1. Each module 6 when plugged into one of the primary locations 4 is operated under the control of the central processing unit 2. Some of the modules 6 may control the switching operation between a bank of additional extension lines, while others may control the switching of additional exchange lines to respective extension lines, which are controlled under the operation of respective modules 6, while other ¢03 05 modules may control other housekeeping functions of the PBX 1, as well as certain features of respective feature telephones connected to the PBX 1. The operation of such PBXs with modules under the control of a central processing unit will be well known to those skilled in the art, and it is not intended to describe the actual switching and control functions of the modules 6, since it does not form part of the invention. Each module 6 is provided with a multiple contact plug connector 7 for engaging the socket connector 5 of the primary location 4 at which the module 6 is to be connected.

A primary bus 8 interconnects the central processing unit 2 with the respective socket connectors 5 at the primary locations 4 for interconnecting the modules 6, which are plugged into socket connectors 5 at the respective primary locations 4, with the central processing unit 2. In this embodiment of the invention, communication between the central processing unit 2 and the respective modules 6 is carried out under SPI communication protocol. The primary bus 8 comprises two serial data communication lines 9 and 10, namely, a data-in line 9 and a data-out line 10, a clock line 11 for a clock signal, and a chip enable line 12 for carrying a chip enable signal for enabling the commencement of data transfer between the addressed module 6 and the central processing unit 2. The primary bus 8 also comprises three chip select lines 13 for carrying three bit primary address codes of the primary locations 4 for sequentially selecting the modules 6 at the respective primary locations 4.

Each primary location 4 is provided with a three bit primary address storing register 14 for storing the primary address code of the corresponding primary location 4.

Each primary address register 14 is connected to the corresponding socket connector 5 by a three bit bus for facilitating reading of the primary address code from the primary address register 14 through the socket connector 5 by the module 6 connected thereto.

Referring now in particular to Fig. 2, each module 6 comprises a plurality of selectively addressable secondary locations 15, each comprising a device 16, which may be a controller, or other suitable device for controlling corresponding functions IE 0 ϊ 0 5 4 4 and features of the module 6 and the PBX 1. Such devices 16 located at the secondary locations may, for example, be Sicofi devices, SPCX devices, EEPROMs or any other such device which would typically be located in such a module for communicating with a central processing unit and for operating under the control of the central processing unit.

A programmable logic device 17 is located in each module 6 for directing communication between the devices 16 at the secondary locations 15 and the central processing unit 2 under the control ofthe central processing unit 2. Secondary buses 18 communicate the devices 16 at the secondary locations 15 with the programmable logic device 17 of each module 6. A primary address code comparing means is provided in the programmable logic device 17 of each module 6 and comprises a primary address code comparator 19. The primary address code comparator 19 reads the primary address code in the primary address register 14 of the corresponding primary location 4 through the corresponding plug and socket connectors 7 and 5 for comparison with primary address codes on the chip select lines 13 of the primary bus 8, for determining if the module 6 is being addressed by the central processing unit 2.

A reading means, namely, a read/write circuit 20 in each programmable logic device 17 is responsive to the corresponding comparator 19 determining that the module 6 is being addressed for reading a secondary address code from data on the data-out line 10 for ascertaining which ofthe secondary locations 15 in the module 6 is being addressed by the central processing unit 2. In this embodiment ofthe invention the secondary address code is a three bit code provided by the three least significant bits of the first byte of a data communication to the module 6, the primary address code of which appears on the chip select lines 13.

A switching circuit 22 in the programmable logic device 17 of each module 6 comprises a main switch means, namely, a seven position main switch circuit 23 for sequentially switching the secondary buses 18 ofthe secondary locations 15 through to the data lines 9 and 10 for the transfer of data between each addressed secondary location 15 and the central processing unit 2. Serial data on the data-out ΙΕ ο 3 Ο 5 4 4 line 10 is read by the read/write circuit 20 and is written by the read/write circuit 20 to the main switch circuit 23 on a serial data line 24 for switching through to the addressed secondary location 15. A serial data line 25 communicates the main switch circuit 23 with the read/write circuit 20 for facilitating reading data from the addressed secondary location 15, and writing the data to the central processing unit 2 on the data-in line 9.

A secondary switch means, namely, a secondary switch 27 located in the switching circuit 22 of each module 6 switches the chip enable line 12 of the primary bus 8 to the main switch circuit 23 which in turn switches the chip enable line 12 to the selected one of the secondary locations 15. The secondary switch 27 is operable under the control of the comparator 19, and is held closed under the control of the comparator 19 for so long as the primary address code of the primary location 4 into which the module 6 is plugged remains on the chip select lines 13. In this way, the chip enable signal is transferred through to the device 16 at the selected secondary location 15, and is held switched through to the selected secondary location 15 for so long as the primary address code corresponding to that module 6 remains on the chip select lines 13. The chip enable signal from the chip enable line 12 is also read by the read/write circuit 20 for determining the commencement of data transfer between the central processing unit 2 and the selected secondary location 15. Additionally, the programmable logic device 17 may be addressed directly by the central processing unit 2, and may itself communicate directly with the central processing unit 2.

Although not illustrated, the clock signal on the clock line 11 is applied to each module 6 which is coupled to the PBX 1 through the corresponding plug/socket connector 7, 5, and the clock signal is appropriately applied to the programmable logic device 17, the read/write circuit 20 and the devices 16 at the secondary locations 15, and to any other components of each module 6 as will be well understood by those skilled in the art.

In use, as modules 6 are connected into the PBX 1 at primary locations 4 thereof for expanding the PBX 1 to, for example, increase the extension and/or exchange line IE 0 3 05 4 4 capacity of the PBX 1, or for handling other aspects of communication or operation of feature telephones connected to the PBX 1, the primary address code of the primary location to which each module 6 is connected is written to the central processing unit 2, and cross-referenced with the identity of the module 6. In this way the central processing unit 2 can identify and address the module 6 by the appropriate three bit primary address code of the primary location to which the module 6 is connected. On a primary address code being placed on the chip select lines 13 by the central processing unit 2, each module 6 connected to a corresponding one of the primary locations 4 compares the primary address code with the primary address code stored in the primary address register 14 of the primary location 4 to which the module 6 is connected. On the comparator 19 of the programmable logic device 17 determining that the primary address code corresponds with the primary address code of the primary location 4, and on the chip enable signal going low, indicating the commencement of data transfer, the read/write circuit 20 of the programmable logic device 17 reads the first byte of data on the data-out line 10 for determining the secondary address of the secondary location 15 being addressed by the central processing unit 2. In response to the secondary address the main switch circuit 23 is operated for switching the selected secondary location 15 to the data lines 9 and 10 of the primary bus 8 for transfer of data between the central processing unit 2 and the selected secondary location 15.

Additionally, the secondary switch 27 is operated for switching the chip enable signal from the chip enable line 12 through the main switch circuit 23 to the selected secondary location 15. The secondary switch 27 is held closed under the control of the comparator 19 for so long as the primary address code of the primary location 4 remains on the chip select lines 13. Thus, data is transferred between the central processing unit 2 and the selected secondary location 15. By retaining the chip enable line 12 connected through to the selected secondary location 15 during the transfer of data between the central processing unit 2 and the secondary location 15, the chip enable signal on the chip enable line 12 may be toggled by the central processing unit 2 for carrying out specific data transfers in accordance with predetermined protocols between the central processing unit 2 and the selected secondary location 15 after data transfer has commenced. ΙΕΟ J 054 4 On the transfer of data being completed, the central processing unit 2 pulls the signal on the chip enable line 12 high indicating termination of data transfer. Additionally, the three bit primary address code is removed from the chip select lines 13 and the secondary switch 27 is opened, thereby isolating the selected secondary location 15 from the chip enable line 12.

Communication is re-established between the central processing unit 2 and a selected one of the secondary locations 15 of the module 6 at the primary location 4 by applying the appropriate three bit primary address code to the chip select lines 13, and communication commences again as already described. Needless to say, other modules 6 connected to other primary locations 4 are addressed and operate in a similar manner, when the primary address codes corresponding to primary locations 4 of those modules 6 are applied by the central processing unit 2 to the chip select lines 13.

The advantages of the invention are many. A particularly important advantage of the invention is that each module can be readily identified and addressed by the central processing unit by simply looking up the primary address code of the primary location to which the module to be addressed is connected. The module is then addressed by the primary address code of the primary location to which the module is connected. Thus, there is no danger of modules being incorrectly addressed, since all that is required to address each module is the primary address code of the primary location to which the module is connected.

While the primary bus has been described as comprising three chip select lines, any number of chip select lines may be provided from two upwards. The greater the number of chip select lines the greater the number of primary address codes which can be provided, and thus the greater the number of primary locations 4 which may be selectively addressed. In this embodiment of the invention, by providing three chip select lines 13, seven primary locations can be selectively addressed allowing for one default value of the primary address code, which typically is zero, zero, zero. Indeed, in certain cases a single chip select line may be provided, however, this IE Ο 3 Ο 5 4 4 would only provide for selectively addressing two primary locations without a default value.

It will also be appreciated that the secondary address code of the respective 5 secondary locations in each module may be provided by any number of bits, from one upwards. The more bits which are provided, the greater the number of secondary locations which may be addressed. By providing three bits in the first data word in the transfer of data provides for seven secondary locations 15 to be addressed, allowing for one default value, which typically is zero, zero, zero. io While communication between the central processing unit and the modules connected to the primary locations 4 has been described as being carried out under the SPI communications protocol, any other suitable communications protocol may be used, and it will of course be appreciated by those skilled in the art that the number of serial data communication lines and the need for a chip enable line will be dependent on the communications protocol being used.

Claims (15)

Claims

1. A PBX comprising a central processing unit, a plurality of selectively addressable primary locations for receiving respective plug-in modules, a connecting means provided at each primary location for receiving one of the plug-in modules, a primary bus interconnecting the central processing unit with the primary locations for communicating the central processing unit with each module plugged into a corresponding one of the primary locations, the primary bus comprising at least two chip select lines for carrying primary address codes of the respective primary locations for selecting the modules plugged into the respective primary locations, a chip enable line for carrying a chip enable signal for initiating communication between the central processing unit and the selected module, and at least one serial data communication line for communicating data between the central processing unit and the selected module in a desired communication protocol, at least one plug-in module being plugged into the connecting means at one of the primary locations, each module comprising a plurality of selectively addressable secondary locations, a programmable logic device comprising a comparing means for comparing primary address codes on the primary bus with the primary address code of the corresponding primary location, a reading means responsive to the comparing means determining that a primary address code compares with the primary address code of the corresponding primary location, for reading a secondary address code at a predetermined location in a data signal on the primary bus for identifying one of the secondary locations of the module with which data is to be communicated with the central processing unit, a main switch means responsive to the programmable logic device for coupling the selected one of the secondary locations with the central processing unit through the at least one serial data communication line of the primary bus, and a secondary switch means responsive to the programmable logic device for coupling the selected one of the secondary locations with the chip enable line of the primary bus.

2. A PBX as claimed in Claim 1 in which the secondary switch means is responsive to the primary address code remaining on the chip select lines of the primary bus for retaining the selected one of the secondary locations coupled to the chip enable line of the primary bus. IF 0 3 0 5 4 4

3. A PBX as claimed in Claim 1 or 2 in which the primary bus comprises three chip select lines for accommodating seven primary address codes.

4. A PBX as claimed in any preceding claim in which each secondary address code is a three bit code.

5. A PBX as claimed in any preceding claim in which the predetermined location of the data signal at which each secondary address code is located comprises the first byte of the data signal.

6. A PBX as claimed in Claim 5 in which each secondary address code is provided by the three least significant bits of the data signal.

7. A PBX as claimed in any preceding claim in which each secondary location is connected to the programmable logic device by a secondary bus.

8. A PBX as claimed in Claim 7 in which each secondary bus comprises one line which is coupled to the secondary switch means.

9. A PBX as claimed in Claim 7 or 8 in which the lines of each secondary bus are coupled to the main switch means.

10. A PBX as claimed in any preceding claim in which each primary location comprises a primary address register for storing the primary address code of the corresponding primary location.

11. A PBX as claimed in Claim 10 in which the comparing means of each module reads the primary address code of the primary location to which the module is plugged in from the corresponding primary address register through the connecting means.

12. A PBX substantially as described herein with reference to and as illustrated IE 0 3 05 4 4 in the accompanying drawings.

13. A method for selectively communicating between a central processing unit of a PBX and a plurality of plug-in modules plugged into corresponding selectively addressable primary locations ofthe PBX, wherein each module comprises a plurality of selectively addressable secondary locations, the method comprising the steps of providing a primary bus interconnecting the central processing unit with the primary locations, the primary bus comprising at least two chip select lines for carrying primary address codes of the respective primary locations for selecting the modules plugged into the respective primary locations, a chip enable line for carrying a chip enable signal for enabling a selected one ofthe secondary locations for initiating communication between the central processing unit and the selected secondary location, and at least one serial data communication line for communicating data between the central processing unit and the selected modules in a desired communication protocol, the method comprising the further steps of operating each module plugged into a primary location for comparing primary address codes on the chip select lines of the primary bus with the primary address code of the corresponding primary location for determining if the module plugged into the primary location is being addressed, operating an addressed module for reading a secondary address at a predetermined location in a data signal on the primary bus for identifying the secondary location of the addressed module with which data is to be communicated with the central processing unit, and switching the selected secondary location to the at least one serial data communication line of the primary bus, and separately switching the selected secondary location to the chip enable line of the primary bus for providing a chip enable signal to the secondary location for indicating the commencement of data transfer.

14. A method as claimed in Claim 13 in which the selected secondary location is switched to the chip enable line for so long as the primary address code of the primary location to which the module is connected remains on the chip select lines.

15. A method for selectively communicating between a central processing unit of a PBX and a plurality of modules releasably plugged into a plurality of selectively IE Ο 3 05 4 4 addressable primary locations of the PBX, the method being substantially as described herein with reference to and as illustrated in the accompanying drawings.