IES83266Y1 - A private branch exchange, and a method for selectively communicating the central processing unit with respective modules in the private branch exchange - Google Patents

Description

A private branch exchange, and a method for selectively communicating the central processing unit with respective modules in the private branch exchange” The present invention relates to a private branch exchange (PBX), and in particular to a PBX having a central processing unit and a plurality of locations for receiving plug-in modules whereby the central processing unit is selectively communicable with the plug-in modules.

According to the invention, there is provided a PBX having a central processing unit and a plurality of selectively addressable primary locations for receiving respective plug-in modules, wherein each module comprises a plurality of selectively addressable secondary locations, a bus interconnecting the central processing unit with the primary locations for communicating the central processing unit with the respective modules at the primary locations in a desired communication protocol, the bus comprising an at least two parallel chip select tracks for carrying a binary code corresponding to a primary code of a selected one of the primary locations for selecting the module plugged into the primary location, appropriate number of serial data tracks for communicating data in the desired communication protocol, a chip enable track for carrying a chip enable signal for enabling a selected one of the secondary locations of a module in a selected primary location for enabling data transfer between the secondary location and the central processing unit, a releasable connecting means at each primary location for connecting a module to the bus at the primary location, a programmable logic device connected to the connecting means at least some of the primary locations, each programmable logic device comprising a comparing means for comparing a code on the chip select tracks with the primary code of the primary location to which the programmable logic device is connected, a reading means responsive to the comparing means detecting a chip select code corresponding to the primary code of the primary location for reading a secondary address at a predetermined location in a data signal received from the central processing unit for identifying the secondary location in the module with which data is to be transferred the central processing unit, a main switch means for switching data signals between the central processing unit and the addressed secondary location in response to the secondary address, and a secondary switch means responsive to the secondary address read from the predetermined location in the data signal for switching the selected secondary locations to the chip enable track for applying the chip enable signal thereon to the secondary location.

In one embodiment of the invention, the secondary switch means is responsive to the chip select signal remaining on the chip select tracks for retaining the selected secondary locations switched through to the chip enable track.

In one embodiment of the invention, three chip select tracks are provided for providing seven primary address codes.

In another embodiment of the invention, three bits of the data signal at the predetermined location are reserved for the secondary address for facilitating addressing of seven selected secondary locations.

In a further embodiment of the invention, the predetermined location of the data signal is provided in the first eight bits of the data word, and preferably, the secondary address is provided by the three least significant bits (LSBs) of the first eight bits of the data word.

Preferably, the programmable logic devices are incorporated in at least some of the modules, and preferably, in all of the modules, one programmable logic device being provided in each of the modules.

Additionally, the invention provides a method for selectively communicating between a central processing unit of a PBX and a plurality of modules releasably plugged into a plurality of selectively addressable primary locations, wherein each module comprises a plurality of selectively addressable secondary locations, the method comprising the steps of providing a bus interconnecting the PBX with the respective primary locations, wherein each bus is provided with at least two parallel chip select tracks for carrying a binary code corresponding to a primary code of a selected one of the primary locations for selecting a module plugged into the primary location, an appropriate number of data tracks for communicating in the desired communicating protocol, a chip enable track for carrying a chip enable signal for enabling a selected one of the secondary locations for the transfer of data between the selected secondary location and the central processing unit, a clock track for carrying a carrying a clock signal, the method comprising the further steps of comparing a code received on the chip select tracks with the primary code of the primary location for determining if the primary location is being addressed, reading a secondary address at a predetermined location in a data signal communicated to the module at the selected primary location for identifying the secondary location with which data is to be transferred between the central processing unit and the secondary location, switching the selected secondary location to each data track, and switching the selected secondary location to the chip enable track for enabling the selected secondary location for the commencement of data transfer.

Preferably, the selected secondary location is switched to the chip enable track for so long as the chip select signal of the primary location to which the module is connected remains on the chip select tracks.

The invention will be more clearly understood from the following description of an embodiment thereof, which is given by way of example only, with reference to the accompanying drawings in which: Fig. 1 is a block representation of a PBX according to the invention, and Fig. 2 is a circuit diagram of a module of the PBX illustrated connected into the PBX.

Referring to the drawings, there is illustrated a PBX according to the invention indicated generally by the reference numeral 1. The PBX comprises a central processing unit 2 which controls the operation of the PBX 1 as well as the setting up of connections between respective extension lines, and between the respective extension lines and exchange lines. Such PBXs will be well known to those skilled in the art, and it is not intended to describe the actual functioning of the PBX 1 for switching calls between extension lines and extension and exchange lines. The PBX 1 comprises a plurality of primary locations 4, each comprising a multiple contact socket 5 for selectively and releasably receiving modules 6 which operate under the control of the microprocessor 1 for controlling the functioning of various aspects of the PBX 1. For example, some of the modules 6 may control the switching operation between a bank of, for example, eight extension lines, while others may control the switching of exchange lines to respective extension lines controlled under the operation of respective modules 6, while other modules may control other housekeeping functions of the PBX 1 and certain features of respective feature telephones connected to the PBX 1. The operation of such PBXs with modules under the control of a central processing unit will be well known to those skilled in the art, and it is not intended to describe the actual functions of the modules 6.

A main communicating bus 8 interconnects the central processing unit 2 with the respective sockets 5 at the primary locations 4 for interconnecting modules 6 which are plugged into sockets 5 at the respective primary locations 4 with the central processing unit 2. In this embodiment of the invention, communication between the central processing unit and the respective modules 6 is carried out under SPI communications protocol, and the main communicating bus 8 comprises two serial data tracks 9 and 10, namely, a data in track 9 and a data out track 10, a clock track 11 for a clock signal, a chip enable track 12 for carrying a chip enable signal for enabling the commencement of data transfer between the addressed module 6 and the central processing unit 2. The main communicating bus 8 also comprises three parallel chip select tracks 13 for carrying three bit primary address codes for selecting the module 6 at a selected primary location 8, the primary address code of which corresponds to the primary address code on the chip select tracks 13. The data tracks 9 and 10, the clock track 11, the chip enable track 12 and the chip select tracks 13 are connected to the sockets 5 at the respective primary locations 4. Each primary location is provided with a three bit address stored in a register 14 at the primary location 4, and the register 14 is connected to the socket 5 by three wires corresponding to the respective bits for in turn connecting to a module 6 connected to the socket 5.

Each module 6 comprises a plurality of selectively addressable secondary locations , which may be controllers or other suitable devices for controlling corresponding parts of the modules 6. The devices located at the secondary locations 15 may, for example, be a Sicofi device, an SPCX device, an EEPROM, or any other such device which would typically be located in such a module for communication with a central processing unit and for operating under the control of the central processing unit. A programmable logic device 17 in each module 6 is connected to the register 14 of the primary location through the socket 5 for reading the primary code therefrom, and is connected to the main communicating bus 8 through the socket 5.

The programmable logic devices reads signals from the main communicating bus 8 through the socket 5 for determining if the module 6 is being addressed and the secondary location 15 of the module 6 being addressed, and the programmable logic device 17 controls the transfer of data with the secondary location being addressed.

The programmable logic device 17 may also be addressed by the central processing unit 2 and will itself communicate with the central processing unit 2.

The programmable logic device 17 of each module 6 comprises a comparing means, namely, a comparing circuit 19 for comparing the three bit codes on the three chip select tracks 13 with the stored three bit primary code in the register 14. On the comparing circuit 19 determining that a primary code on the chip select tracks 13 corresponds with the stored primary code in the register 14, a reading means, namely, a reading circuit 20 reads the first eight bits of data being transmitted on the data in track 9 to the module 6 for reading a secondary address code provided in the three least significant bits of the first eight bits of data for identifying the secondary location 15 with which data is to be transferred with the central processing unit 2.

A switching circuit 22 in the programmable logic device 17 comprises a main switch means, namely, a seven position main switch circuit 23 for switching the addressed secondary location 15 through to the data buses 9 and 10 for the transfer of data between the address secondary location 15 and the central processing unit 2. Serial data from the data in track 9 is transferred from the reading circuit 20 to the main switching circuit 22, and in turn to the main switch circuit 23 on a serial line 24, while a serial line 25 communicates serial data on the data out track 10 between the reading circuit 20 and the switching circuit 22 and in turn the main switch circuit 23.

A secondary switch means, namely, a secondary switch 27 in the switching circuit 22 switches the chip enable signal from the chip enable track 12 to the main switch circuit 23, which in turn switches the chip enable signal to the selected one of the secondary locations 15. The secondary switch 27is operable under the control of the comparing circuit 19, and is held closed under the control of the comparing circuit 19 for so long as the primary address code of the primary location 4 into which the module 6 is plugged remains on the chip select tracks 13. In this way the chip enable signal is transferred through to the selected location 15, and is held switched through to the selected central location 15 for so long as the primary address code remains on the chip select tracks 13. The chip enable signal from the chip enable track 12 is also read by the reading circuit 20 for determining the commencement of data transfer between the central processing unit 2 and the selected secondary location 15.

In use, as modules 6 are connected into the PBX 1 at primary locations 4 thereof, as the PBX 1 is being expanded to, for example, handle a larger number of extension lines or exchange lines or for handling other aspects of communication or operation of feature telephones connected to the PBX 1, the identity and the primary location to which each module is connected is written to the central processing unit 2, so that the central processing unit 2 can address the module by the three bit primary code of the primary location 4 on the chip select tracks 13. On a primary code being placed on the chip select tracks 13 by the central processing unit 2, each module connected to a primary location 4 compares the primary code with the primary code of the primary location 4 stored in the register 14 to which the module 6 is connected. On the comparing circuit 19 of the primary logic device 17 determining that the primary code corresponds with the primary code of the primary location 4, and on the chip enable signal going low, indicating the commencement of data transfer, the reading circuit 20 of the programmable logic device 17 reads the first eight bits of data on the data in track 9 for determining the secondary address of the secondary location 15 being addressed by the central processing unit 2. In response to the secondary address the main switch circuit 23 is operated for switching the selected secondary location 15 to the data buses 9 and 10 for transfer of data between the central processing unit 2 and the selected secondary location 15.

Additionally, the secondary switch 27 is operated for switching the chip enable signal from the chip enable track 12 directly to the selected secondary location 15. The secondary switch 27 is held closed under the control of the comparing circuit 19 for so long as the primary code of the primary location 4 remains on the chip select tracks 13. Thus, data is transferred between the central processing unit 2 and the selected secondary location 15. By retaining the chip enable track 12 connected through to the selected secondary location 15 during the transfer of data between the central processing unit 2 and the secondary location 15 the chip enable signal 12 may be toggled by the central processing unit for carrying out specific data transfers in accordance with predetermined protocols between the central processing unit 2 and the selected secondary location 15 after data transfer has commenced.

On the transfer of data being completed, the central processing unit 2 pulls the signal on the chip enable track 12 high indicating termination of data transfer.

Additionally, the three bit primary code is removed from the chip select tracks 13 and the secondary switch 27 is opened.

Communication is re—established between the central processing unit 2 and a selected one of the secondary locations 15 of the module 6 at the primary location 4 by applying the appropriate three bit primary code to the chip select tracks 13, and communication commences again as already described. Needless to say, other modules connected to other primary locations 4 are addressed and operate in a similar manner when the primary codes corresponding to those primary locations 4 into which other modules 6 are connected is applied by the central processing unit 2 to the chip select tracks 12.

While the main communicating bus has been described as comprising three chip select tracks, any number of chip select tracks may be provided from two upwards.

The greater the number of tracks the higher the primary code which can be applied, and thus the greater number of primary locations 4 which may be selectively addressed. In this embodiment of the invention, by providing three chip select tracks 13, seven primary locations can be selectively addressed allowing for one default value of the primary code, which typically is zero, zero, zero. Indeed, in certain cases a single chip select track may be provided, however, this would only provide for selectively addressing two primary locations without a default value.

It will also be appreciated that the secondary address code of the respective secondary locations in each module may be provided by any number of bits, from one upwards. The more bits which are provided, the greater the number of secondary locations which may be addressed. By providing three bits in the data word being transferred provides for seven secondary locations 15 to be addressed, allowing for one default value, which typically is zero, zero, zero.

While communication between the central processing unit and the modules connected to the primary locations 4 has been described as being carried out under the SPI communications protocol, any other suitable communications protocol may be used, and it will of course be appreciated by those skilled in the art that the number of data tracks and the need for a chip enable track will be dependent on the communications protocol being used.

The invention is not limited to the embodiment hereinbefore described which may be varied in construction and detail.

Claims (5)

Claims

1. A PBX having a central processing unit and a plurality of selectively addressable primary locations for receiving respective plug—in modules, wherein each module comprises a plurality of selectively addressable secondary locations, a bus interconnecting the central processing unit with the primary locations for communicating the central processing unit with the respective modules at the primary locations in a desired communication protocol, the bus comprising an at least two parallel chip select tracks for carrying a binary code corresponding to a primary code of a selected one of the primary locations for selecting the module plugged into the primary location, appropriate number of serial data tracks for communicating data in the desired communication protocol, a chip enable track for carrying a chip enable signal for enabling a selected one of the secondary locations of a module in a selected primary location for enabling data transfer between the secondary location and the central processing unit, a releasable connecting means at each primary location for connecting a module to the bus at the primary location, a programmable logic device connected to the connecting means at least some of the primary locations, each programmable logic device comprising a comparing means for comparing a code on the chip select tracks with the primary code of the primary location to which the programmable logic device is connected, a reading means responsive to the comparing means detecting a chip select code corresponding to the primary code of the primary location for reading a secondary address at a predetermined location in a data signal received from the central processing unit for identifying the secondary location in the module with which data is to be transferred with the central processing unit, a main switch means for switching data signals between the central processing unit and the addressed secondary location in response to the secondary address, and a secondary switch means responsive to the secondary address read from the predetermined location in the data signal for switching the selected secondary locations to the chip enable track for applying the chip enable signal thereon to the secondary location.

2. A PBX as claimed in Claim 1 in which the secondary switch means is responsive to the chip select signal remaining on the chip select tracks for retaining the selected secondary locations switched through to the chip enable track.

3. A PBX substantially as described herein with reference to and as illustrated in the accompanying drawings.

4. A method for selectively communicating between a central processing unit of a PBX and a plurality of modules releasably plugged into a plurality of selectively addressable primary locations, wherein each module comprises a plurality of selectively addressable secondary locations, the method comprising the steps of providing a bus interconnecting the PBX with the respective primary locations, wherein each bus is provided with at least two parallel chip select tracks for carrying a binary code corresponding to a primary code of a selected one of the primary locations for selecting a module plugged into the primary location, an appropriate number of data tracks for communicating in the desired communicating protocol, a chip enable track for carrying a chip enable signal for enabling a selected one of the secondary locations for the transfer of data between the selected secondary location and the central processing unit, a clock track for carrying a clock signal, the method comprising the further steps of comparing a code received on the chip select tracks with the primary code of the primary location for determining if the primary location is being addressed, reading a secondary address at a predetermined location in a data signal communicated to the module at the selected primary location for identifying the secondary location with which data is to be transferred between the central processing unit and the secondary location, switching the selected secondary location to each data track, and switching the selected secondary location to the chip enable track for enabling the selected secondary location for the commencement of data transfer.

5. A method for selectively communicating between a central processing unit of a PBX and a plurality of modules releasably plugged into a plurality of selectively addressable primary locations of the PBX, the method being substantially as described herein with reference to and as illustrated in the accompanying drawings. F.F. GORMAN & CO.