ID27634A - Kemudahan memperbaharui register dalam sebuah prosesor yang rusak - Google Patents

Kemudahan memperbaharui register dalam sebuah prosesor yang rusak

Info

Publication number
ID27634A
ID27634A IDP20000824A ID20000824A ID27634A ID 27634 A ID27634 A ID 27634A ID P20000824 A IDP20000824 A ID P20000824A ID 20000824 A ID20000824 A ID 20000824A ID 27634 A ID27634 A ID 27634A
Authority
ID
Indonesia
Prior art keywords
renewing
register
ease
broken
processor
Prior art date
Application number
IDP20000824A
Other languages
English (en)
Inventor
Robert Greg Mcdonald
Peichun Peter Liu
Christopher Hans Olson
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of ID27634A publication Critical patent/ID27634A/id

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
IDP20000824A 1999-10-14 2000-09-25 Kemudahan memperbaharui register dalam sebuah prosesor yang rusak ID27634A (id)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/417,824 US6484251B1 (en) 1999-10-14 1999-10-14 Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processor

Publications (1)

Publication Number Publication Date
ID27634A true ID27634A (id) 2001-04-19

Family

ID=23655531

Family Applications (1)

Application Number Title Priority Date Filing Date
IDP20000824A ID27634A (id) 1999-10-14 2000-09-25 Kemudahan memperbaharui register dalam sebuah prosesor yang rusak

Country Status (5)

Country Link
US (1) US6484251B1 (id)
JP (1) JP3519047B2 (id)
CA (1) CA2317080C (id)
GB (1) GB2360375B (id)
ID (1) ID27634A (id)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10358358B4 (de) * 2003-12-12 2008-05-08 Infineon Technologies Ag Mikroprozessoranordnung und Verfahren zum Betreiben einer Mikroprozessoranordnung
US7996662B2 (en) * 2005-11-17 2011-08-09 Apple Inc. Floating point status/control register encodings for speculative register field
WO2008020271A1 (en) * 2006-08-18 2008-02-21 Freescale Semiconductor, Inc. Method for performing plurality of bit operations and a device having plurality of bit operations capabilities
US8412862B2 (en) * 2008-12-18 2013-04-02 International Business Machines Corporation Direct memory access transfer efficiency
US9311087B2 (en) * 2012-12-21 2016-04-12 Arm Limited Sticky bit update within a speculative execution processing environment
US9444735B2 (en) * 2014-02-27 2016-09-13 Cisco Technology, Inc. Contextual summarization tag and type match using network subnetting

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5287503A (en) * 1991-09-27 1994-02-15 Sun Microsystems, Inc. System having control registers coupled to a bus whereby addresses on the bus select a control register and a function to be performed on the control register
US5974240A (en) * 1995-06-07 1999-10-26 International Business Machines Corporation Method and system for buffering condition code data in a data processing system having out-of-order and speculative instruction execution
US5764970A (en) * 1995-11-20 1998-06-09 International Business Machines Corporation Method and apparatus for supporting speculative branch and link/branch on count instructions
US5826070A (en) * 1996-08-30 1998-10-20 International Business Machines Corporation Apparatus and method for maintaining status flags and condition codes using a renaming technique in an out of order floating point execution unit
US6021488A (en) * 1997-09-23 2000-02-01 International Business Machines Corp. Data processing system having an apparatus for tracking a status of an out-of-order operation and method thereof
US6151669A (en) * 1998-10-10 2000-11-21 Institute For The Development Of Emerging Architectures, L.L.C. Methods and apparatus for efficient control of floating-point status register

Also Published As

Publication number Publication date
GB2360375B (en) 2004-03-31
US6484251B1 (en) 2002-11-19
GB0023163D0 (en) 2000-11-01
JP2001117770A (ja) 2001-04-27
JP3519047B2 (ja) 2004-04-12
CA2317080A1 (en) 2001-04-14
CA2317080C (en) 2004-06-08
GB2360375A (en) 2001-09-19

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