HUT52263A - Recognition system - Google Patents

Description

-a e tsl.llxánv party party ^ oj »eljlrá * t n * an ilő, na ^ v aeanyiréfü task done ir-í ινίνί ·? write * '* and vsz / rlee for a separate Jsen skala-v rendering system vone.tkoaik · .zenfel il the system is structured in such a way that «atly is capable of generating artificial intelligence at a * <ae level and simultaneously controlling and controlling the event for the purpose.

the prior art relates to the large range of views that ni form · τλ i -nzi artificial intelligence.

ⁱ , current main focus is clearly on siots «« is a new kind of programming software araelvek srr ** v ^ a-sk is intended to unify the mountain.invo numerical pings - with a degree of .aestersé / es intelligence.

inden Artificial Intelligence Hardware Engineer. The requirement is to provide more efficient female agents for managing the complexity and rapid growth of program areas and et cetera, which occurs through the so-called parallelism of processing, ideally because of the name reel. like peak death times · *, etc. Research methods, such as relevant data bases, are content controllable amongst other methods that emerge as a result of the enhancement made by Vnor to achieve significant performance.

Artificial intelligence systems can be divided from n'Ovid's and deductive or inductive thinking into two areas, with the prominent obligation of such systems to bring about the means of this learning.

During this time, the literature had been in trial for some time. Recognizing modeling, or brain models, are the resulting procedures expressed individually and invariably ® L®probe; ?, ·. »- It seems like it is applied · Examples can be found in the pair processing where the need for a week> .lighter connection is met on 'doolean n * ^ models · 4» en models n traditional software program Inside the neuron 1 You have housings that «mimic some brain cell activity. As a result, attention is being paid & improving memory usage on disk priming and "actual" memory layouts, where ever faster salt paths and tilt oscillations are required through very high speed integrated rocks / VHTSTC / ? »Rzenide and gallium eluminium arsenide. Multiple times tens of nanoseconds of memory input tears are achieved with such media, but to process information by cladding such media, using parallel processing techniques to weave pond systems still outperforms 3.? a system with a maximum throughput of milliseconds, the human brain.

Despite the limitations of flax, designers have shown a reluctance to deviate from the traditional design approach and, accordingly, have developed patterns of restrictive workmanship such as:

- Developing software for use with serial computers

- adding coprocessors to serial machines

- development of '/ L ^r T circuits containing a large number of processor elements in neural networks.

some systems were capable of low levels

- 4 -, · '·: ·· ·:

* · · * To access Ulap, stored logical interface microcircuits, neural networks, multi-threading, supernatural circuits tjví 'hold menia, but eddi? -a, e aesters, .er; the creators of intelligence have not developed machines that can learn alone · It seems that the main factor that contributes to this inability is ho'-v the designers use the basic structures embedded in Von Weumann's architecture and hopy 9 masters? to achieve a high level of intelligence in a taste pond and provide other structures that provide a more conducive environment for the education of a * i.ae within a gene structure.

DESCRIPTION OF THE INVENTION Accordingly, it is an object of the present invention to provide a recognition system that provides an appropriate environment for controlling a large amount of complex response using efficient parallel processing at a relatively low cost.

According to one aspect of the present invention, there is provided a recognition system for opening and controlling a large number of complex tasks using parallel processing consisting of:

several individual intelligent professors, each capable of performing specific tasks;

memory means capable of receiving information for transmission to said ^# 3 processor by said intelligent processor;

in order to overwrite the writing of said information, the state of the .as'nóriij · π line memory © lemmel bir, arranged in predetermined locations, is the storage space for said information;

devices for the coupling of an intelligent nrocessor with another, with the exclusion of direct connection; and mediation means for feeding information to and out of the scalar;

wherein said intelligent processors include a control device dedicated to organizing said information fed from said mediation means to said memory harbors and increasing said memory means to said memory devices, having regard to the knowledge of the system and said processors and intermediaries. dedicated to its organization and management.

Separate intelligent processors are milletype and are capable of performing tasks associated with specific tasks mentioned above.

preferably the &lt; c &gt; &lt; / RTI &gt; information is retained within the predetermined locations of said memory.

Preferably said memory device is subdivided into separate: .analyses related to the tasks of said intelligent processors, which encapsulates information about one or other of the data in the corresponding memory part.

- 6 - f,:, is stored to facilitate the relative arrangement of the information stored in said memory device x.

preferably, access to at least some of the hosted smart printers is limited to pre-defined memory portions. \ z Specific intelligent processors for which this access is restricted can be selectively allocated.

preferably, said memory elements are addressed with content rather than addressing.

Preferably, said memory device is capable of substantially simultaneously accessing said intelligent processors by at least some of the information provided by the intelligent processors that are required to access this memory device.

The said memory device includes a main memory for storing permanent information and an active memory for storing temporary information.

preferably said memory is capable of substantially simultaneously being accessed by said control means by said and selected other said intelligent processors and capable of providing information from and extracting said active memory.

Preferably, said main memory comprises a matrix of said memory elements interconnected to permit independent and simultaneous access thereto by a plurality of intel yoke processors operating in parallel.

preferably said guiding means comprises a

- 7 control devices - the operation of the basic operation of this system © Benőre - - "worth" and in view of its task, the information stored in the memory of this task, and an executive control tool for controlling and managing the overall operation of the system being all the information cached in the memory device.

preferably, said management device is capable of monitoring said intelligent processors and mediation devices for unexpected events and maintaining knowledge of the operational status of the system and controlling selected information between said intelligent processors and mediation devices.

preferably, said management device is also capable of interacting with said intelligent processors, memory devices and executing control means for resolving said unexpected events.

preferably, said managing body is able to arrange the execution of its task in a hierarchical manner according to the urgency of the operation.

preferably, the executive control agent sulfur selectively interacts with said intelligent processors, memory devices, and said management bodies to resolve unexpected events, which requires knowledge of said executive control device, o .it provides access to all information within said memory devices. , and requires you to verify that your system is working properly.

preferably said transmitting means includes a space for aborting certain types of information input to the system, such as said information means, and exiting the types of information. to other said intelligent processors in such a way that other types of said information are still readily accessible to said warning means.

Slowly, this is a huge amount of active memory from time to time, which is a short duration □ of memory and a picture memory to use ?. short-term memory is dedicated to:

/ i / temporarily storing temporary information of short duration for use by an observer for use by said executing control device;

/ ti / providing said main memory with the nietv transition information selected by said executing control device, thereby converting the selected temporary information into durable information; and / or iii) destroying other temporary information not belonging to said executive control device after a short period of time;

worth said image memory dedicating to:

(1) temporary interim information from said management device for temporary monitoring and soliciting by said executing control device;

iii) providing said short-term mamoris with selected transient information selected by said executing control means, thereby converting said selected temporary information into short-term temporary information; and

/ III / the time-stamping of other temporary information not included in the blood door control essence of an instant over a temporary period of time, said transient period being less than said short time period artsm. : shoot any of the mentioned smart processors. obsession ®aok many of your i * companions »»

to complete the data:

/ V graph processing for creating and displaying graphs; / U / · Recognition processing to decode an encoded input * _. ^ for recognition purposes; / Sits / output processing for intelligent processing of information for output purposes, transmitted via said drafting means; /arc/ an input processor for intelligent processing of information for input purposes obtained through said intermediary means; / V / processing telecommunications to control off-site bidirectional connections with intelligent devices. yi smart processors can carry these above / i / - / v / to perform additional tasks as well. _i drawing rivid description Λ find the girl will be more understandable its features following description, ·, in light of, description «

The sketch attached is done with reference to skate? in which the system components are arranged in a human SVG structure.

Proceedings to take the bowl bowl

'.'in as shown in the region, "from 11 recognition systems by b &n?" »» more intelligent processors including typical tasks aagukbs Capture processors and Π control escort, e & y jn ^ power device, ⁿ mediation device and contact areas / no wall shown / @z Among intel * ligent processors. The λ system is interconnected by the intermediary device D and e ^ y. kai? he structure.

xi a and B each processor interprets a microprocessor and local persistent memory to accommodate the solid state structure and controls the processor ndk> d4 and perform the necessary processing functions according to the solid structure and application software instructions .

present siettestesitósben the λ processors funkciónáliean 13 graphics processing means, the 15 identity to also Nero device, u 17 outputs ^ triturated device, 19 input processing means, and 21 a speech synthesis ^f in the device working with the 23 speech felisnerés processing means digs n 25 image processing powers of the s. «Are arranged in the meantime.

*., z The primary function of the processors, which provide a means for locking the graphics processing 13, is to process, produce and display this graphical information · for output y. · Rafi’tus for outgoing structures.

executed according to an intact program, containing appropriate algorithms for the processor and stored in a solid structure 47 of the dedicated system. If the tight-lean »13 orocessor is immediately sulfuric to access the allowable portion of the memory device J's brain, it has resolved to store information needed for the 4nroessors.

The primary function of the processors that provide the means for identity recognition, as, is to decode an encoded input of jansk, such as a security page, fingerprint, azo image, etc., for the purpose of this identity recognition. and these processors have a computer program that stores xie-like algorithms stored in the solid state structure 47 and provides instant access to a permitted portion of the u memory e-'if required. 17 output processors are secured by intelligently tilting the information to an output purpose to be transmitted through the intermediary device D to an external structure. As in the previous processes, this processor has a word processing software dedicated to accessing the stored algorithm 47 in solid state with instant access to the allowed portions of the memory device C, if narrow.

The input processor wn is entrusted with intelligent processing of information received from an external device through an intermediary device, as with the previous processor, the input processor has a software program dedicated thereto containing the algorithm stored in the solid state 47 and } add maturity to the allowed parts of bir «0 .memory device if it does so. ven.

, the functions of other processors 21, 23 and 25 are obvious

- 12 and as in the previous proeeesor, what a female client is ... a computer doctor in the ... jq that stored them in a solid hard drive holds their dedicated algorithms. all a.n. h.a. bir to the aiaoori ^ flavored parts of the ae ^, covered by the vsn.

The 45 external telecommunication processor is also an intelligent processor located at the bottom, outside the system, as one of the external structures · _The basic function of the unified processor is to control bidirectional connections ”and a certain external structure that is intelligent. accordingly, the processor directs a prescribed procedure and communicates with vsn other processors and with the myiaware device through this controlling device.

The contents of the memory device * or a series of xemory elements, arranged in predefined locations, also store information therein. The intended locations of the memory device are divided into separate memory sections, which are generally related to the tasks performed by the smart processor A, so that information about one or more tasks to be performed by the smart processor is stored in the appropriate memory. t.irolv.i, it facilitates the relative arrangement of information within the ms-aory device.

Λ memory device macros a main memory and? an active memory. main memory retains a length of 27 memory for storing persistent information, and active memory ts.rt-sl.2sz has 29 rivid of June memory and 51 image memory, making it a duplicate capability for storing through-time information for various periods of time. Permanent memory s 47 provided with a solid structure.

The 27 honsau tarta.au: ae: ioria are such exports, vni is particularly characteristic of promoting parallel processing · r-'zen particularly? -aetiria is a high-density, readable / writable niara that has single-Tsal matrix interleaved memory elements # The memory elements are interconnected in such a way as to allow simultaneous negation by several different λ and 3 processors. The information can be varied within the prescribed locations of the memory elements. stored such that m ¹ . one of the foregoing locations contains relatively ordered information · X'5 is rendered by an intelligent processor rather than the location of a memory processor which is x'5 a malfunction.

The 27 long-lasting geniuses allow us to store information by providing a knowledge base that is conditionally accessed by a variety of processors and selectively accessible by 3 control devices. in a communication device, © which can act as a tyrant element, can memory elements be included as a tree? communication devices, © which can be read or written by a sensor head, or, optionally, the front could comprise solid state electrical charge storage devices which are cimmed with electronic devices. In addition, memory elements can be used in new shapes of meuori technology, such as laser memories or the like · However, be aware that the & menus are fully interconnected so as to allow two or more cool elements at the same time. me.geimzés more pr.ocesezor 41 tel · 'rv prefer pair.uaaacF meaeria access Ur.otiva -a * ski ar · a <? findings m: Bí' .szmlvz, .'íú.-it olysgi · · Zart <z@t.?k, which does not allow for only one * aiff to look meary i ολ <. · A /. Vascular laser • for aeaori media this is achieved by using a n & ^ ysaámu sensing space and its solid state is meaoria inter. negtostesitée.

r transmits in his father mac the space of 33 i nf no. ^ tion and 39 b8.synth / kin gates to pass .information from the outside to the system and thence. 3a, respectively, are connected to external λ structures such as the output ca. 41, the input 43, and? 45 n.nl-nge? telecommunications processor.

Λ 41 output structures include displays, nvoattata, digital control xiaenets, local oll'oot flags, and the like. Λ Input structures may include local interaction inputs, analog inputs, digital inputs and the like, and telecommunication 45; processor tsrtalaisibat recorder but transmit current clocks for connection to various communications specifications including ainü asynchronous, «ind synchronous specifications such as 1 (3232, 2d -aA current <3« projector, ~ “42 ?, ηγτ.γχ ?, ITC 'T »ürtc and the like.

teimlc relationship 3ahatJ with ^the form of ^the intermediary u, which leads the selective information received by the intermediary device megfelelő ^to the corresponding and 3 intelligent processors.

k is a directional device 55 or two and one executive means 55 or an executive means 57 and a means 57 for executing _the meaning vi. the 55 and the 57 are special intelligent processors that allow the full operation of the slave system to be unlocked by dividing the Irinyi Lake task hierarchically between the slots.

Λ 55 managers relatively higher level of processing, mustard, cint taste; processors, they are basically in the form of a network-like system, aaelv coordinate »all input and output cases in a hierarchical manner · In addition, the supervisor fundamentally controls and i ^ ^ performs basic contact operations within the system. The 37 Values · ® Creator leyna ^ ycbb system intelligence and I have weeks * to check the system's operation and solve unexpected cases with the horse in mind? 1 memory, meanwhile, for the information stored, the functions of the explorer and the intelligent are determined individually by their constant solid structure and can be accessed with the help of traditional software out-of-the-box procedures.

The areas of contact between tz intelligent processors include any suitable means "along or through which communications may be transmitted, such as" means may include lugs for transferring data from one processor to the other "to allow instant contact in such a manner. between connected processors. A single processor may have multiple interfaces to allow multiple processors to share resources

when completing a task.

It can be seen from the foregoing that the relationship / interaction between the various sub-items of the system is highly ordered to facilitate parallel processing at optimum speed. Accordingly, the A 4 ^a B intelli ens processors are arranged so that each processor is immediately z4f4r4s «from» to this any zone can fall into 27 long-term memory as graphically depicted, this hosphere sphere is controlled by a solid structure of continuously coordinated processors, as symbolically depicted in <7 · * 4debonds the processor may be silent for each task 4 '• with 35 stewards and senses · radion over 49 mesh transport networks depicted by arrowed arrows · In addition, interaction between any 4 oroces and 37 inserts 47 through its solid structure and contact areas.

Λ 27 öosezu hold sU memory, as previously described, accessible by belmmelvik \ processor and »37 bells 47 solid! Through Structure. In addition, this long-term .memori »is accessible through 37 networks and by these 35 operators through this networked transport network, © melv direct access route al bir ® 29 and 31 via short terisau and no x would last long for oaaoria 53 and 51 over. The long-term memory is preceded by the selected short-term memory 29 from the short-term memory 29, the processors 37 associated with this task, and the processor 35 defined.

• ·

- —_ · ·· * · ♦

- 17 -::

Picture of 29 short duration memory alone with 37 items? go direct and assume that it is capable of executing. with the organizer and the processors. the short hold-au list 29 essentially includes a removable memory dedicated to temporarily storing short-term temporary information from the request memory 31. zz the information in the memory unit is stored only for a relatively short period of time for art amokiff vuri for purposes of sensory control and selective use, at the discretion of the latter, corresponding to the temporary information stored within the short-term memory 29 is e. y dies after a short period of time, which means that hs a * 7 meant that v should not provide the long term aemori 27 with this information, v * n scrapped from the short term memory unit in the path indicated by arrow 52 after a short period of time. conditional access to short-term memory is provided by ss phys. t processors are provided via these paths 51, which are connected to the network-like transport network 4) via its.

image memory intends to interact directly with these senses alone, and is capable of conditional millet snowserver and processor A, but is solved by information transmitted to it by system 35. The image memory 31 is dedicated to temporarily storing temporary information for a very short period of time, for the purpose of selection by reason 37, at the discretion of the latter. according to you, the image memory holds an out-of-state first-state register that stores information for a transient time

- lei tartö'-aijj, aii soc-c & l Less than 29 short-term memory short before such information dies on and off from the memory via the path indicated by arrow 53. The meaning of the unit 57, as it may wish, monitors the image memory 31 and defines in it information information that is important to the system. The? 9 short-term memory is optional *. provides you with information for further consideration and consideration ·

The intermediary device hat can communicate with the 35 directories or »2 A processors · the direct k'51 cb selflet in the direction of the director is also provided through Gates 59 only for certain types of vw nvert information transmitted through 55 paths. indirect interaction with director 35 is provided through its space 33 with respect to certain types of information obtained from gates 59 via path 57 which are input to a processor. z Millet Indirect Millet is provided by route 59, Switched between herd * and 35, which provides selected information selected by the administrator · í-.In addition, all outgoing information from this system to the 39 entrance / exit gates ven transmitted via the path 55, and selected information input system o v® _lake y 55, y ^ v & _a4 through route 57 to yield v ^ n, depending on the inf> the nature and significance of rn4ció predetermined species.

The deflector 33 acts as a deflector for input information from the intermediary device to the file manager 35 and is responsive to the processors.

\ 35 re '.dszsr is responsible for managing system information 19 • · you may have iBba with most of the system components ·,. which performs four main functions;

/ i / monitoring processors A and deflector 53 for these unexpected events and maintaining c system operational status;

/ 11 / controlling selected information linkage between processors A 'between the relay means r;

/ iii / conditional interaction with the processors, 51 cells, 27 and 29 short-term and long-term memory, and 37 intelligence to resolve unexpected events; and hierarchical ordering of tasks / archives / tasks according to the urgency of the required action ·

In the case of Λ processors, aemories, and intelligence, this is done through 49 networked transport networks, but in the case of 35 deflectors, a different kind of interaction is inherent, which is controlled by the deflector. is monitored, and if important in itself, v> §y for consideration by reason, is copied from the deflector to the conductor 35 via path 59.

- 2-When system 55 recognizes an unexpected event, it can order the unexpected event to be processed in a hierarchical manner with respect to other tasks it has to perform, and resolve the incident as necessary to the appropriate proctor (s), access to memory and / or intelligence through the network-like transport network 49. ~ more than 5> 55 administrators can transmit some of the information they obtain from their observer and administrator duties to the intellect for examination, by transmitting the same directly to the 51 image memory units · in the system · * Ή Intelligence is master and can selectively interact with all With nrocea hair, all g memory devices, and 55 file managers, deer allow intelligence to solve »unexpected events that require knowledge of the system's full operation and information for subordinate management decisions, meaning me, 37 meaning higher there are 35 viral & tlu.n events to solve, only 35 managers.

Fő The main advantage of the invention, as provided by the present embodiment, is that the system has a six-fold structure that enables the composite deductive level of thinking to be provided by artificial means for interpreting and answering a large number of complex cases. very high speed integrated parallel processors and performs group, which has a parallel access gjnr _«t stored information, logical algorithms and powerful layout management tasks, EGV highly ordered execution! task allocation and designation structure.

* η · ο up processing, speeds are achieved by arranging the tilting devices, etc. in a structure that allows parallel processing to be assigned to each processor at the same time · or 3 specific tasks to be performed in parallel with other processors .

Λ In order to further increase speed, in cases where a processor requires access to s main memory, memory mapping is achieved by associating the information with the information content by storing the information in the main memory according to the content rather than by in a chronological arrangement or the like, a processor can then move directly to the memory element containing the information it is looking for, by associating it with information spaces rather than successively through a large amount of unrelated information until the desired information is located in the ee. <ven determined.

another aspect of high speed is the fact that any processor should be able to * access the information you are looking for right away, rather than waiting in line. Not withstanding its use, and using this long-lasting nemori® structure, it allows simultaneous access to memory elements so as to avoid competing for access with other processors.

to facilitate the connection between processors, memory devices and control devices, preferably a symbolic language® is used. Also, this system

2?

various fw.nkc'Os my duties as the elders of Jalcé o ^ si-n, as to these .me £ K.J nny i té s the contacts nlatt.

Consequently, a core? · »:,. this token © «language is used to make my memory followers, but · execute Isi ·» *? · things are great.

In my present .me embodiment, the various algorithms of the processing tools are written as symbolic pro rra, dedicated to the processors to operate in accordance with the function of the salt, which they are required to execute. stored in structure vsnnsí.

Finally, to achieve high speed processing of the system, it is necessary to use a highly ordered and organized execution task definition system such as provided by the control means described herein.

be aware that the scope of the girl you find is not limited to the cajátoe embodiment described here. In particular, the. functions or tasks performed by processors are not strictly limited to those described herein; they may also carry with them other tasks that may be necessary for a particular application. Also, my same processor can have different tasks without having to change the system so that the system would need to be changed, thus allowing the use of a single machine for four different adults and the bee being able to maintain optimal performance.

Claims (17)

1. 'is the recognition system a large number of complex tasks? control, using parallel processing, aoely includes the following.k.a. multiple kJlJnill) intelligent processors, aaelvtk r.any one. capable of performing cumbersome tasks; aeaoriil tools, © lkaimaima i.nfor. receiving and transmitting information for examination by said inteigen processor, arranged in locations provided on said memory means of a plurality of pairs of memory elements for storing said information; means for interconnecting one intelligent processor with another, allowing remote contact between them; and input and output means for transmitting and transmitting means therefrom; wherein said intelligent processors include a control means dedicated to organizing said information and directing said information to said aearic devices, from said ealitPtt relay means to said aeoria devices, having regard to the knowledge of the system and devoting and organizing contacts to said processors and mz said mediation tools are excluded. The recognition system of claim 1, wherein said information is relational. is stored within the aforesaid locations of said. '.. Gloria devices. 5 · \ 2. i «Highlight recognition system in which • ml of drunk memory memory * Flavors up. o? ztv% information about the external memory parts associated with the tasks of the intelligent processors, smi being stored in an appropriate memory part of one or the other task, to facilitate the relative ordering of information stored in the ζlitfctt memory device. The recognition system of claim 3, wherein the access of at least some of said intelligent processors is limited to a predetermined amount of memory. Recognition system according to any one of the preceding claims, wherein said memory elements are rather addressed by their content rather than by their location. Recognition system according to any one of the preceding claims, wherein said memory device is capable of being accessed substantially at least "by some" of said intelligent processors, including said control means and providing information therefrom. 7. A recognition system according to any one of the preceding claims, wherein said memory utilizes a main memory for storing persistent information and an active memory for storing temporary information. The recognition system of claim 7, wherein said meorian is capable of substantially simultaneously accessing said control device and a selected other device? is judged by i '^ ns processors and is capable of being provided with information -in words? as mentioned in active memory. The recognition system according to claim 7 or 8, wherein: ··········································· -.l'tset memory tool sulfur srrn so that it can be accessed at the same time as accessing the main memory n ^ W, so that it is supplied with information from there. Recognition system according to any one of claims 1 to 7, wherein said main memory store a matrix of nasalized memory elements that are interconnected to provide independent and simultaneous access thereto. by an intelligent processaor. 11. A recognized system as claimed in any one of the preceding claims wherein said control means comprises a management means for controlling and managing the age of said system for frying biscuits with respect to said information stored on the '*' items stored in said blanking device. some, and an executive control device. To control and manage the overall operation of the system, given all the information stored in the memory device. 12. The recognition system of claim 11, wherein said management device is able to check said intelligent processors and mediation devices for unexpected vessels, and to maintain recognition of the poppy state of the system and control communication of selected information. mentioned above among intelligent processors and mediation devices. The recognition system of claim 12, wherein said management device is also capable of interacting with said intelligent processors, memory means and executing control means for resolving said unexpected events. 14. a recognition system according to any one of claims 11 to 13, wherein? ./. said memory device is a sulfur hierarchical arrangement of tasks according to the urgency of this operation · Recognition system according to any one of claims 15 to 4, 11 to 14, wherein the control device is sulfur? * zelectively milling in with said processors, memory means and said management device, the unexpected seed solver requiring knowledge of said executing control device, as provided by its ability to access all information in said memory device and verify system operation. Recognition system according to any one of claims λ 11 to 15, wherein said transmitting device includes a space for directing certain types of information entering the system directly to said management entity and directing other types of information directly to other intelligent processors such that however, other types of said information may still be provided by said managing body. 17. The bar item according to claims 11 to 16, and 7 to IC. The recognition system dependent on any one of claims 1 to 5, wherein the active memory '-.s mentioned above' comprises an argument short-term memory and a burn image memory, from which said short-term memory is dedicated to: ···· EE ···· • · · · · • ··· · • · · " ·· · · / 1 / short-term transfer.aenatí temporary storage! · «For the purpose of controlling and updating said executive control device; / 11 / supplying said main information with certain transition information selected by said executing control means, thereby converting the selected interim information into durable information; and and said image memory is dedicated to: / 1 / temporarily storing music information from the operating device for control and selective user control by said executing control device; / U / * Providing said short duration memory with certain temporary information selected by said executing control means, thereby converting said selected temporary information into short duration information; and / 111 / After the e & y transition period, no other event information. An uplink system according to any one of the preceding claims, wherein said intelligent processors store means for performing any or all of the following tasks: / 1 / some kind of graphic processing to create and display graphs; ♦ ··· ee • · · ········································································································································ / Ii / output processing for intelligent processing of this information for output purposes, transmitted via said mediation means; / iv / input processing to perform intelligent processing of information to input targets obtained through said mediation means; / ▼ / processing telecommunications for controlling bidirectional connections outside the system with intelligent structures. 19. Basically, the recognition system described here with proper reference: ·. cr & pushed drawing.