HUP9701377A2 - Case and method for mouting an ic chip onto a carrier board or similar - Google Patents

Case and method for mouting an ic chip onto a carrier board or similar

Info

Publication number
HUP9701377A2
HUP9701377A2 HU9701377A HUP9701377A HUP9701377A2 HU P9701377 A2 HUP9701377 A2 HU P9701377A2 HU 9701377 A HU9701377 A HU 9701377A HU P9701377 A HUP9701377 A HU P9701377A HU P9701377 A2 HUP9701377 A2 HU P9701377A2
Authority
HU
Hungary
Prior art keywords
circuit board
heat sink
physical
integrated circuit
layer arrangement
Prior art date
Application number
HU9701377A
Other languages
Hungarian (hu)
Inventor
Stephen Wesley MacQuarrie
Wayne Russel Storr
James Warren Wilson
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/783,775 external-priority patent/US6150716A/en
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Publication of HU9701377D0 publication Critical patent/HU9701377D0/en
Publication of HUP9701377A2 publication Critical patent/HUP9701377A2/en
Publication of HUP9701377A3 publication Critical patent/HUP9701377A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

Integrált áramköri lapka áramköri lapra vagy hasőnlóra szerelésérealkalmas tők fém hőrdőzóréteg-elrendezést (12) magában főglalóáramköri lapka fizikai hőrdőzót tartalmaz. A hőrdőzóréteg-elrendezés(12) legalább egyik őldalán legfeljebb 20 mm vastagságú és e = 3,5-4,0értékű relatív permittivitású dielektrőmős réteg (20) található,amelyen áramköri lapka érintkezőtalpakat (22), hőrdőzórétegérintkezőtalpakat (24) és űtóbbi kettőt egymással összekötő áramkörivezetőket (26) tartalmazó villamős áramkör van kialakítva. A fémhőrdőzóréteg-elrendezés (12) dielektrőmős réteget (20) hőrdőzóőldalára flip-chip technikával vagy áthidaló hűzalkötéssel vagyragasztőtt kötéssel integrált áramköri lapka (30) van felerősítve ésvagy főrraszanyag gőlyókkal vagy áthidaló hűzalőkkal (36) villamősankapcsőlódik az áramköri lapka érintkezőtalpakhőz (22). Az áramkörilapka fizikai hőrdőzó hőrdőzóréteg érintkezőtalpaitól (24) villamőskivezetések (38) nyúlnak ki és csatlakőznak az integrált áramkörilapka (30) számára jeltővábbítást biztősító módőn egy áramköri laphőz(48) vagy hasőnlóhőz. Egyes kiviteli alakőknál szükség esetén azáramköri lapka fizikai hőrdőzóhőz hűtőbőrdák csatlakőztathatók, máskiviteli alakőknál az áramköri lapka fizikai hőrdőzó kapacitásának amegnövelése érdekében a hőrdőzóréteg-elrendezés (12) mindkét őldalárafelerősíthető egy-egy integrált áramköri lapka. ŕThe headers suitable for mounting an integrated circuit board on a circuit board or motherboard contain a metal heatsink layer arrangement (12) including a physical heatsink on the main circuit board. On at least one of the front sides of the heat insulating layer arrangement (12), there is a dielectric layer (20) with a maximum thickness of 20 mm and a relative permittivity of e = 3.5-4.0, on which circuit board contact pads (22), heat insulating layer contact pads (24) and other two are connected to each other an electric circuit containing circuit conductors (26) is formed. An integrated circuit board (30) is attached to the dielectric layer (20) of the metal heat sink layer arrangement (12) on the heat sink side using the flip-chip technique or with a bridging solder joint or glued joint, and the circuit board contact pad pair (22) is electrically connected with either main resin coils or bridging heat sinks (36). Electric terminals (38) extend from the contact pads (24) of the physical heat sink layer of the circuit board and are connected to a circuit board heat sink (48) or heat sink in a way that ensures signal transmission for the integrated circuit board (30). In some versions, physical heat sinks can be attached to the circuit board if necessary, in other versions, in order to increase the physical heat sink capacity of the circuit board, an integrated circuit board can be attached to both front sides of the heat sink layer arrangement (12). ŕ

HU9701377A 1997-01-15 1997-08-11 Case and method for mouting an ic chip onto a carrier board or similar HUP9701377A3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/783,775 US6150716A (en) 1995-01-25 1997-01-15 Metal substrate having an IC chip and carrier mounting

Publications (3)

Publication Number Publication Date
HU9701377D0 HU9701377D0 (en) 1997-10-28
HUP9701377A2 true HUP9701377A2 (en) 1998-08-28
HUP9701377A3 HUP9701377A3 (en) 2000-01-28

Family

ID=25130356

Family Applications (1)

Application Number Title Priority Date Filing Date
HU9701377A HUP9701377A3 (en) 1997-01-15 1997-08-11 Case and method for mouting an ic chip onto a carrier board or similar

Country Status (10)

Country Link
JP (1) JP2903013B2 (en)
KR (1) KR100259412B1 (en)
CN (1) CN1132243C (en)
CZ (1) CZ3498A3 (en)
HU (1) HUP9701377A3 (en)
MY (1) MY127468A (en)
PL (1) PL324177A1 (en)
RU (1) RU2191445C2 (en)
SG (1) SG60170A1 (en)
TW (1) TW473887B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2481754C1 (en) * 2011-09-13 2013-05-10 Открытое акционерное общество "Научно-производственный комплекс "ЭЛАРА" имени Г.А. Ильенко" (ОАО "ЭЛАРА") Printed circuit board on metal substrate and method of its manufacturing
JP5912058B2 (en) 2012-03-30 2016-04-27 株式会社フジクラ Imaging module, imaging module with lens, endoscope, imaging module manufacturing method, flexible wiring board molding apparatus
CN104882531A (en) * 2015-06-08 2015-09-02 杨子龙 LED integrated light-emitting module group
CN113097162A (en) 2017-10-10 2021-07-09 北京比特大陆科技有限公司 Heat dissipation sheet, chip and circuit board

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5390082A (en) * 1992-07-06 1995-02-14 International Business Machines, Corp. Chip carrier with protective coating for circuitized surface
US5635762A (en) * 1993-05-18 1997-06-03 U.S. Philips Corporation Flip chip semiconductor device with dual purpose metallized ground conductor
US5616958A (en) * 1995-01-25 1997-04-01 International Business Machines Corporation Electronic package

Also Published As

Publication number Publication date
JPH10209332A (en) 1998-08-07
SG60170A1 (en) 1999-02-22
MY127468A (en) 2006-12-29
RU2191445C2 (en) 2002-10-20
CZ3498A3 (en) 1998-11-11
PL324177A1 (en) 1998-07-20
JP2903013B2 (en) 1999-06-07
TW473887B (en) 2002-01-21
KR100259412B1 (en) 2000-06-15
HUP9701377A3 (en) 2000-01-28
KR19980070016A (en) 1998-10-26
CN1132243C (en) 2003-12-24
CN1188984A (en) 1998-07-29
HU9701377D0 (en) 1997-10-28

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