CN1188984A - Metal substrate having IC chip and carrier mounting - Google Patents
Metal substrate having IC chip and carrier mounting Download PDFInfo
- Publication number
- CN1188984A CN1188984A CN97125492A CN97125492A CN1188984A CN 1188984 A CN1188984 A CN 1188984A CN 97125492 A CN97125492 A CN 97125492A CN 97125492 A CN97125492 A CN 97125492A CN 1188984 A CN1188984 A CN 1188984A
- Authority
- CN
- China
- Prior art keywords
- chip
- integrated circuit
- definition
- substrate
- installation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 29
- 239000002184 metal Substances 0.000 title claims abstract description 29
- 238000000576 coating method Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 12
- 238000009434 installation Methods 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 15
- 238000005538 encapsulation Methods 0.000 claims description 12
- 238000003466 welding Methods 0.000 claims description 12
- 239000004642 Polyimide Substances 0.000 claims description 9
- 229920001721 polyimide Polymers 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000000853 adhesive Substances 0.000 abstract 1
- 230000001070 adhesive effect Effects 0.000 abstract 1
- 239000003822 epoxy resin Substances 0.000 description 10
- 229920000647 polyepoxide Polymers 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 229910001374 Invar Inorganic materials 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 1
- 239000004810 polytetrafluoroethylene Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
A package for mounting an integrated circuit chip to a circuit board or the like is provided. The package includes a chip carrier which has a metal substrate. A dielectric coating is provided on at least one of the faces, which preferably is less than about 20 microns in thickness, and preferably has a dielectric constant from about 3.5 to about 4.0. Electrical circuitry is disposed on the dielectric coating, said circuitry including chip mounting pads, connection pads and circuit traces connecting the chip mounting pads to the connection pads. An IC chip is mounted by flip chip or wire bonding or adhesive connection on the face of the metal substrate which has the dielectric coating thereon. Chips can be mounted on both sides of the chip carrier to increase the capacity of the chip carrier.
Description
The present invention relates to be used to be installed in the encapsulation of the integrated circuit on chip-carrier (IC) chip above the circuit board etc., or rather, relate to and be provided for being called as the chip of flat packaging outward appearance and the technology that bearing is installed.
The conventional bearing that the chip that uses is for many years installed is metallized ceramic flat packaging structure.Although pottery has a lot of good performances, it uses certain shortcoming again.For example, pottery does not have good especially thermal conduction characteristic, therefore usually needs innovative technology to remove heat.Pottery also needs to handle modestly, particularly before heating with prevent the cracking.In addition, pottery needs the operation of several roads to form required ceramic support, has caused quite high cost like this.
People have the effort that replaces ceramic support with organic bearing always, replace as the epoxy resin of filling with glass, and it has the characteristic similar to circuit board, i.e. identical materials.Although overcome some shortcomings of ceramic support, this type of bearing still has some shortcomings, as conductibility very poor with form required circuit fine rule (fine line) in abutment surface to be connected the chip on it and signal reached circuit board and some technical problems when spreading out of circuit board.
Thereby a main purpose of the present invention provides and a kind of integrated circuit is installed on the encapsulation of circuit board, and it comprises having the thermal conduction characteristic that improved and the chip-carrier of excellent electric characteristics, includes the floating earth plane.
According to the present invention, provide to be used for integrated circuit (IC) chip is installed in encapsulation on circuit board etc.Described encapsulation comprises that one has the chip-carrier of first and second apparent surface's metal substrates.Described metal substrate preferably is made up of the copper product of the equal chromium plating of its one or both sides.At least on the one side dielectric coated is arranged in its each face, dielectric coated is polyimides preferably.The thickness of described dielectric coated preferably is no more than 20 microns, and preferably has 3.5 to 4.0 dielectric constant.Circuits System is arranged on the dielectric coated, and described circuit comprises that chip installs pad, connection pads and be connected the trace (trace) of described chip installation pad and connection pads.
The IC chip is mounted thereon the surface of the described metal substrate with dielectric coated.This installation can be to utilize scolder to do the flip-chip welding of machinery or electrical interconnect, or is installed in the sticking card of described chip on the described circuit board and utilizes the line weldering to be electrically connected.In both cases, described IC chip is connected electrically on the described chip installation pad by soldered ball or line weldering welding.The connection pads of electrical lead from the chip-carrier extended and is connected to circuit board etc. and go up on the corresponding pad, so that provide I/O signal for the IC chip.In some embodiments, additional heat sink on described chip-carrier, and among some embodiment, chip also can be installed in the both sides of described chip-carrier, to improve the capacity of described chip-carrier.
Fig. 1 is the flat sheet of the bottom view of the part of described integrated circuit (IC) chip and chip-carrier encapsulation, has removed some part and is simplified for clearly demonstrating;
Fig. 2 is the longitudinal sectional drawing of described chip of Fig. 1 and chip-carrier, has shown the described encapsulation that is installed on the circuit board;
Fig. 3 is for being installed on the longitudinal sectional drawing of another embodiment of the encapsulation on the circuit board according to the present invention;
Fig. 4 is the longitudinal sectional drawing that utilizes the another embodiment of the present invention of additional heat sink;
Fig. 5 is for utilizing additional heat sink, but disposes the longitudinal sectional drawing of different another embodiment of the present invention;
Fig. 6 is the longitudinal sectional drawing that utilizes the chip on described bearing two sides and also utilized the another embodiment of the present invention of additional heat sink.
Consult accompanying drawing now, i.e. Fig. 1 and Fig. 2 have shown the embodiment of integrated circuit (IC) Chip Packaging that is installed on circuit board according to the present invention among the figure.
Described encapsulation comprises that one is designated as 10 chip-carrier usually, and the latter comprises metal substrate 12.Described metal substrate preferably has the copper core 14 that is coated with chromium 16 and 18 its apparent surface.Yet, to describe as present, can use other metals, as fine copper, invar, copper-invar-copper (C-I-C) and other this type of materials.Yet, because it is very good electric conductor and has good thermal conduction characteristic so that can be used as fin that the copper of chromium plating is optimal material.Usually, described substrate 12 thickness are about 0.025 inch, although thickness can be in the scope about to 0.04 inch about 0.010 inch.Be thinner than 0.010 inch thick substrate and significantly reduced the efficient of described substrate, make encapsulation volume huge and heavy and surpass 0.040 inch thick substrate, and more significant heat radiation is not provided as fin.
Thin layer dielectric material 20 is applied on the chromium 16 on a surface of described substrate 10, and it preferably has 3.5 to 4.0 dielectric constant.Best medium is a polyimides.Described polyimides preferably sprays, and makes to apply uniform shallow layer.Yet polyimides can spin coating.Can use other media, as epoxy resin, polytetrafluoroethylene etc.; Yet, be preferably polyimides, because its easy coating, have uniform coating and can remain in substrate surface and thickness is reduced to 6 microns and do not had big defective, this is preferable thickness.Yet operable thickness is up to about 20 microns.Coating is got over Bao Yuehao, because core body is used as a floating earth plane, medium is thin more, and the efficient of described metal substrate 12 is high more.In fact, the thickness of polyimides 20 is about 6 microns, and the efficient of described substrate 12 is about 95% of the heat efficiency, and is 20 microns at the thickness of polyamide 20, and the heat efficiency is reduced to about 50%.Thereby 20 microns thickness is the maximum ga(u)ge of the medium 20 that allowed, and preferably 6 microns or thinner thickness.
In the circuit forming surface system of described medium 20, this Circuits System comprises chip anchor pad 22, connection pads 24 and circuit trace 26.Described circuit preferably forms by the photosensitive corrosion-resisting technics that utilizes known spraying depositing metal of industry and close etching technology.Usually described metal spraying is deposited to about 6 microns thickness; Yet the thickness of metal can be in the scope about to 8 microns about 4 microns.Book can cause that in 4 microns thickness Circuits System is discontinuous, can not produce microcircuit (fine circuit) characteristic and be thicker than 8 microns thickness.
Formed there to be conductive epoxy resin (conductive epoxy) 32 to be fixed in the IC chip 30 on described substrate 12 surfaces.Described IC chip 30 has a plurality of I/O contact points 34, and the latter is connected to chip anchor pad 22 by means of metal wire welding lead 36.Described connection pads 24 has electrical lead wire 38.Form described pad 22 and 24 and trace 26 after, coating can be the protective finish 42 of polyimides.Yet, can use many other coatings, as epoxy resin.Can adopt method for printing screen that described coating is made pattern, perhaps,, then can adopt photoetching technique to form the pattern of coating if used photosensitive coating.Described protective finish 42 is applied on the described circuit trace 26, is exposed to outer to connect and stay chip anchor pad 22 and connection pads 24.
After described IC chip 30 was fixed in described substrate 12 and has added described electrical lead wire 38 with epoxy resin 32, the whole surface applied of described substrate 12 was with epoxy encapsulant 44.
For the encapsulation of described chip and chip-carrier is installed on the circuit board, described electrical lead wire 38 is fixed on the contact point 46 on the circuit board 48.
The use of described metal substrate 12 provides several advantages than metallized ceramic substrate.One of them is the relative flexibility of described metal substrate 12, reduced like this that the heat relative with ceramic support departs from or mechanical treatment due to the tendency of cracking, particularly without heat treated (green) state.Another significant advantage is the good thermal conduction characteristic of described metal 12, and it allows heat more effectively to scatter and disappear rapidly than ceramic substrate.Also have, described metal substrate provides unsteady ground plane for contact point and Circuits System, and it is effective especially under the situation of the film dielectric layer of 6 micron grade.
The factor that must consider is that the thermal coefficient of expansion between described IC30 and the described bearing 10 has remarkable difference owing to described metal substrate 12.The IC chip that is formed by silicon has the thermal coefficient of expansion (CTE) of scope about 3-4 PPM/degree (ppm/ ℃), and the thermal coefficient of expansion of copper is 18ppm/ ℃ scope.For reducing the risk of the inefficacy that causes by hot error, be necessary to guarantee that chip is extremely thin, thereby increase their flexibility.In fact, described chip is necessary to be no more than 20 micron thickness, and preferably less than 18 microns.Utilization is lower than the chip of this limit, and the very soft flexibility that has conductive epoxy resin that described chip is installed of utilization itself is guaranteed.It has reduced because thermal cycle causes the tendency of damage.Certainly, select the different materials of substrate 12, the error of the thermal coefficient of expansion of chip 30 and substrate 12 as described in can reducing as copper-invar-copper or invar.
Fig. 3 has shown another embodiment of the present invention, wherein can utilize flip chip bonding to fetch the encapsulation that forms described bearing and chip.As seen from Figure 3, provide the IC chip 52 that is installed on soldered ball 54 on the described chip anchor pad 22.As the conventional method in this class upside-down mounting is installed, between described chip 52 and the bearing 12 reinforced epoxy 56 is being set around the described soldered ball 54.This reinforced epoxy helps prevent the loss that is caused by hot error.In this embodiment, around the apparent surface of the end of described substrate 12 and described substrate 12, megohmite insulant 58 is arranged so that go between 60 with described substrate 12 electric insulations.In this case, lead-in wire 60 is connected to contact point 46 on the circuit board 48 with connection pads 24.
Additional heat can be utilized embodiment shown in Figure 4 if desired, has wherein fixed additional heat sink at the opposite side of the described substrate 12 that is fixed with chip.The epoxy resin 63 of described fin available conductive is fixing in a well-known manner.Fig. 4 has shown that also how upside-down mounting welding chip 52 is welded in the same side of described bearing with metal wire welding chip 30.
Fig. 5 has shown another embodiment, and additional heat sink 62 wherein is set, but in the case, the epoxy resin 63 of described fin conductibility is fixed in the top of the chip of described epoxy resin 44 sealings.
Fig. 6 has shown an embodiment, wherein can chip be set in the both sides of described chip-carrier 10.This embodiment is used for upside-down mounting welding procedure as shown in Figure 3 the chip of the both sides of described substrate.Certainly, the both sides chip can utilize the metal wire welding, or a side is used the metal wire solder technology and opposite side use upside-down mounting welding procedure.In this case, fin 62 selects to be fixed in a side, though if the space allows, can fin be set in both sides.
Thereby, most preferred embodiment of the present invention has been described.Yet, know above description, can understand only work usefulness for example of this description, the invention is not restricted to specific embodiment described herein, under the situation that does not deviate from the true spirit of the present invention described in hereinafter claims, can make and variously rearrange, revise and substitute.
Claims (23)
1. one kind is installed on the encapsulation of circuit board or the like with integrated circuit (IC) chip, it is characterized in that comprising:
Chip-carrier, described chip-carrier comprise metal substrate and have first and second apparent surfaces,
At least the dielectric coated on one of described surface,
Described dielectric coated thickness is no more than 20 microns;
Described dielectric coated is provided with Circuits System, and described Circuits System has chip pad is installed, connection pads and the circuit trace that is connected described chip installation pad and described connection pads;
Be installed on the integrated circuit (IC) chip on a described surface of described substrate,
Described integrated circuit has the I/O contact point;
Connect the above I/O contact point of described integrated circuit and described chip being electrically connected of pad is installed; And
The electrical lead wire that extends out from described connection pads is to provide I/O signal to described integrated circuit or by described integrated circuit.
2. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that described dielectric material is a polyimides.
3. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that described integrated circuit (IC) chip is solder-connected to described chip with metal wire pad is installed.
4. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that described integrated circuit (IC) chip is to receive described chip installation pad repeatedly in the upside-down mounting welding.
5. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that described metal substrate comprises that copper layer and described integrated circuit (IC) chip thickness are no more than 20 microns.
6. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that described dielectric material has about 3.5 the dielectric constant to about 4.0.
7. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that the thickness of described dielectric layer is no more than 6 microns.
8. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that described metal substrate is a plating chrome on copper layer.
9. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that dielectric material, and there is Circuits System on described substrate two surfaces, and integrated circuit (IC) chip is installed in described substrate two surfaces on two surfaces of described substrate.
10. as the integrated circuit dress envelope of definition in the claim 1, it is characterized in that fin is fixed on described chip-carrier.
11. the integrated circuit dress envelope as definition in the claim 1 is characterized in that described fin is fixed in the surface of described substrate, chip is not installed on it.
12. the integrated circuit dress envelope as definition in the claim 1 is characterized in that described fin is fixed on the surface of described substrate, has a chip to be installed on it.
13. the integrated circuit dress envelope as definition in the claim 1 is characterized in that circuit board or the like is connected to described electrical lead wire.
14. the method for integrated circuit (IC) chip is installed, it is characterized in that may further comprise the steps:
Chip-carrier is set, and described chip-carrier comprises metal substrate and has first and second apparent surfaces,
In one of described at least surface coating media coating,
Described dielectric coated thickness is no more than 20 microns;
Form Circuits System on described dielectric coated, described Circuits System has chip pad, connection pads and the circuit trace that is connected described installation pad and described connection pads is installed;
Formation has the integrated circuit (IC) chip of I/O contact point;
In the described described integrated circuit (IC) chip of mounted on surface of described substrate, pad is installed to be electrically connected the described I/O contact point and the described chip that connect on the described integrated circuit;
Connection from described connection pads electrical lead wire so that provide I/O signal to described integrated circuit (IC) chip or by described integrated circuit (IC) chip.
15. the method as the installation integrated circuit (IC) chip of definition in the claim 14 is characterized in that described dielectric material is a polyimides.
16., it is characterized in that described integrated circuit (IC) chip is welded to connect to described chip installation pad with metal wire as the method for the installation integrated circuit (IC) chip of definition in the claim 14.
17., it is characterized in that described integrated circuit (IC) chip is to be connected to described chip installation pad in the upside-down mounting welding as the method for the installation integrated circuit (IC) chip of definition in the claim 14.
18. the method as the installation integrated circuit (IC) chip of definition in the claim 14 is characterized in that the thickness of described dielectric layer is no more than 6 microns.
19. method as the installation integrated circuit (IC) chip of definition in the claim 14, it is characterized in that dielectric material is coated on described substrate two surfaces, and on two surfaces of described substrate, form Circuits System, and on two surfaces of described substrate, integrated circuit (IC) chip is installed.
20. as the method for the installation integrated circuit (IC) chip of definition in the claim 14, its feature also is fin is fixed on the described chip-carrier.
21. the method as the installation integrated circuit (IC) chip of definition in the claim 20 it is characterized in that described fin is fixed on described substrate surface, and chipless is installed on it.
22. the method as the installation integrated circuit (IC) chip of definition in the claim 20 is characterized in that described fin is fixed on described substrate surface, has a chip to be installed on it.
23. the method as the installation integrated circuit (IC) chip of definition in the claim 20 is characterized in that described electrical lead is connected on the pad of circuit board or the like.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US783775 | 1991-10-29 | ||
| US08/783,775 US6150716A (en) | 1995-01-25 | 1997-01-15 | Metal substrate having an IC chip and carrier mounting |
| US783,775 | 1997-01-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1188984A true CN1188984A (en) | 1998-07-29 |
| CN1132243C CN1132243C (en) | 2003-12-24 |
Family
ID=25130356
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97125492A Expired - Fee Related CN1132243C (en) | 1997-01-15 | 1997-12-12 | Metal substrate having IC chip and carrier mounting |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JP2903013B2 (en) |
| KR (1) | KR100259412B1 (en) |
| CN (1) | CN1132243C (en) |
| CZ (1) | CZ3498A3 (en) |
| HU (1) | HUP9701377A3 (en) |
| MY (1) | MY127468A (en) |
| PL (1) | PL324177A1 (en) |
| RU (1) | RU2191445C2 (en) |
| SG (1) | SG60170A1 (en) |
| TW (1) | TW473887B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016197496A1 (en) * | 2015-06-08 | 2016-12-15 | 唐刚 | Led integrated light-emitting module |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2481754C1 (en) * | 2011-09-13 | 2013-05-10 | Открытое акционерное общество "Научно-производственный комплекс "ЭЛАРА" имени Г.А. Ильенко" (ОАО "ЭЛАРА") | Printed circuit board on metal substrate and method of its manufacturing |
| JP5912058B2 (en) | 2012-03-30 | 2016-04-27 | 株式会社フジクラ | Imaging module, imaging module with lens, endoscope, imaging module manufacturing method, flexible wiring board molding apparatus |
| CN113097162A (en) | 2017-10-10 | 2021-07-09 | 北京比特大陆科技有限公司 | Heat dissipation sheet, chip and circuit board |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5390082A (en) * | 1992-07-06 | 1995-02-14 | International Business Machines, Corp. | Chip carrier with protective coating for circuitized surface |
| US5635762A (en) * | 1993-05-18 | 1997-06-03 | U.S. Philips Corporation | Flip chip semiconductor device with dual purpose metallized ground conductor |
| US5616958A (en) * | 1995-01-25 | 1997-04-01 | International Business Machines Corporation | Electronic package |
-
1997
- 1997-08-11 HU HU9701377A patent/HUP9701377A3/en unknown
- 1997-10-13 KR KR1019970052339A patent/KR100259412B1/en not_active IP Right Cessation
- 1997-12-12 CN CN97125492A patent/CN1132243C/en not_active Expired - Fee Related
- 1997-12-12 MY MYPI97006030A patent/MY127468A/en unknown
- 1997-12-15 SG SG1997004458A patent/SG60170A1/en unknown
-
1998
- 1998-01-06 TW TW087100113A patent/TW473887B/en not_active IP Right Cessation
- 1998-01-07 CZ CZ9834A patent/CZ3498A3/en unknown
- 1998-01-08 PL PL98324177A patent/PL324177A1/en unknown
- 1998-01-09 JP JP10003024A patent/JP2903013B2/en not_active Expired - Fee Related
- 1998-01-14 RU RU98101113/28A patent/RU2191445C2/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016197496A1 (en) * | 2015-06-08 | 2016-12-15 | 唐刚 | Led integrated light-emitting module |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10209332A (en) | 1998-08-07 |
| HUP9701377A2 (en) | 1998-08-28 |
| SG60170A1 (en) | 1999-02-22 |
| MY127468A (en) | 2006-12-29 |
| RU2191445C2 (en) | 2002-10-20 |
| CZ3498A3 (en) | 1998-11-11 |
| PL324177A1 (en) | 1998-07-20 |
| JP2903013B2 (en) | 1999-06-07 |
| TW473887B (en) | 2002-01-21 |
| KR100259412B1 (en) | 2000-06-15 |
| HUP9701377A3 (en) | 2000-01-28 |
| KR19980070016A (en) | 1998-10-26 |
| CN1132243C (en) | 2003-12-24 |
| HU9701377D0 (en) | 1997-10-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950001181B1 (en) | Ultra high density pad array chip carrier | |
| US5569960A (en) | Electronic component, electronic component assembly and electronic component unit | |
| US5367435A (en) | Electronic package structure and method of making same | |
| KR950012658B1 (en) | Semiconductor chip mounting method and substrate structure | |
| US5578525A (en) | Semiconductor device and a fabrication process thereof | |
| US6326696B1 (en) | Electronic package with interconnected chips | |
| TW558921B (en) | Structure and method for fabrication of a leadless chip carrier with embedded inductor | |
| US6131278A (en) | Metal substrate having an IC chip and carrier mounting | |
| US5731636A (en) | Semiconductor bonding package | |
| CN1139297A (en) | Structure and method of coupling substrates | |
| US6831371B1 (en) | Integrated circuit substrate having embedded wire conductors and method therefor | |
| JP2000323516A (en) | Manufacture of wiring substrate, wiring substrate, and semiconductor device | |
| JP3728847B2 (en) | Multi-chip module and manufacturing method thereof | |
| US6528889B1 (en) | Electronic circuit device having adhesion-reinforcing pattern on a circuit board for flip-chip mounting an IC chip | |
| JP2770820B2 (en) | Semiconductor device mounting structure | |
| CN1132243C (en) | Metal substrate having IC chip and carrier mounting | |
| US20020063331A1 (en) | Film carrier semiconductor device | |
| JP3529507B2 (en) | Semiconductor device | |
| JP3297959B2 (en) | Semiconductor device | |
| JPH10112472A (en) | Semiconductor device and its manufacture | |
| JPH10256428A (en) | Semiconductor package | |
| JPH0786340A (en) | Connection of semiconductor element | |
| JPH10256414A (en) | Semiconductor package | |
| JPS60134497A (en) | Circuit board and method of producing same | |
| JP2841825B2 (en) | Hybrid integrated circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20031224 Termination date: 20100112 |