HU189846B - Multifunctional step voltage generator of modifiable wave shape - Google Patents

Abstract

FIELD OF THE INVENTION The present invention relates to a multifunctional step signal generator with variable signal shape. Its field of application is primarily the measurement of controlled semiconductor devices, hereinafter referred to as the devices examined, their current characteristics. The block diagram of the step signal generator according to the invention is shown in Fig. 2, which includes a clock generator (1) whose output (11) is connected to a clock input (20) of the counter (2), an N-bit D / A converter (3) with an analog output ( 30), with control outputs (4; ... 4m) controlling the stair control circuit (4). The step generator is also characterized by a logic network (6j having inputs (6b ... 6bn) to the counter (2) outputs (21 ... 2n), control input (6vl ... 6bm) of the step control circuit (4)) outputs (41 ... 4m), signal outputs (6kl ... 6kn) to the inputs (31 ... 3n) of the D / A converter (s).

Description

Field of the Invention The present invention relates to a multifunctional step signal generator having a modular shape. Its field of application is mainly for the measurement of controlled semiconductor devices, hereinafter referred to as the devices under investigation, and their current-voltage characteristics.

Of the known solutions, the technical level is represented by the TEKTRONIK 576 Curve Tracer, the relevant instruction manual was published in 1970.

The prior art step signal generator is shown in Figure 1, where each unit is: 1 clock generator, 2 counter, 3 D / A converter, 4 step control circuit, 5 stop circuit.

In this solution, the step control circuit 4 compares the output signal of the counter 2 (or, alternatively, the output signal of the D / A converter 3) with a set signal and, when matched, outputs a stop command signal to the stop circuit 5. The stopping circuit 5 resets (stops) the counter 2, the output signal of which is thus changed, and the step control circuit 4 thereby terminates the stop command signal and the counter 2 can be restarted.

The disadvantages of the known solution are:

- the step mark always starts with zero steps and can be set up to an adjustable number of steps, no other setting is possible,

- during the comparison by the stair control circuit, the desired or the desired signal is displayed for a short time. a set number of steps greater than one step, and special care must be taken to avoid interference with the output signal,

- the stopping circuit often requires a time extension of the command signal from the step control circuit, usually by analogue methods,

- the counter's zeroing (gate) gate is reserved for normal operation, so that it can be used to stop the step signal completely, or not by using additional circuits, e.g. emergency stop,

- the step generator operates with dynamic signals beyond the starting clock, with all their problems (speed, synchronization, sensitivity to disturbances, etc.).

The object of the present invention is to eliminate the disadvantages of the prior art and to provide a multifunctional step signal generator whose output signal can be modified by a built-in program or external control, the output signal is free of interfering pulses and the desired signal is generated by static signals.

The present invention is based on the recognition that when the counter, the D / A converter and the step control circuit are connected to a properly formed logic network, the shape of the step signal at the output of the D / A converter can be modified according to a built-in fixed or variable logic. simple to generate with no interference with static signals.

The known and embodiments of the invention will be described with reference to the drawings, which are as follows:

Fig. 1 is a block diagram of the prior art, Fig. 2 is a block diagram of a step generator according to the invention, Fig. 3 is a preferred embodiment of a logical network.

Fig. 2 is a block diagram of a step generator according to the present invention comprising a clock generator 1 whose output 11 is connected to the clock input 20 of the counter 2, an n-bit 3D / a converter with analog output 30, a step control circuit 4l, ... With 4m outputs. The step signal generator is further characterized by including 6 logic networks having signal inputs 6bl ".. 6bn to the outputs 21, ... 2n of the counter 2, inputs 6vl, ... 6vm to the outputs 4l, ... 4m of the step control circuit 4, 6kl , ... 6kn outputs are connected to the 31, ... 3n inputs of the 3 D / A converter.

The operation of the step generator according to the invention is as follows:

as a result of the signals of the clock generator 1, the counter 2 counts continuously. Counter 2

21n .2n outputs the digital numbers defined by the counter 2 code at the counting rate, e.g. in the case of a 4-bit counter, the outputs 21, ... 24, from the binary OOOO corresponding to the decimal to the binary Iliii corresponding to the decimal 15, and then the process is repeated. The output signals of the counter 2 are displayed in the form of a head integrated into the logic network 6 or a modified (controllable, programmable) logic at the inputs 3l ... 3n of the D / A converter 3 e.g. only the two lower location bits, or only the two upper location bits, while the other two bits are fixed at 0 or 1, and so on. The operation of the logic network 6 is modified by the step control circuit 4.

The output 30 of the D / A converter 3 displays

An analogue output signal corresponding to a bit combination for a 31 ..3n input.

Figure 3 shows a preferred embodiment of the logic network 6, which has four dual-input AND gates 611, 612, 613, 614 having one of the inputs 6bl, 6b2.6b3.6b4 to the outputs of the 4 bit counter 2 and the other 6vl, 6v2, 6v3. , 6v4 input is connected to 4 stage control circuit output. The output of the first AND gate 611 to the one input of the first multiplexer 621, the output of the second AND gate 612 to the other input of the first multiplexer 621 and one to the second multiplexer 622, the third AND port 613 to the second input of the second , the output of the fourth AND gate 614 is connected to the other input of the third multiplexer 623 and to the input of the fourth multiplexer 624, to one of the inputs of the fourth multiplexer 624, and the other input of the fourth multiplexer 624. The multiplexers 621, 622 623, 624 are connected to the signal selector input 6v5 and the prohibitory 6v6 input of the step control circuit 4 outputs. (In Figure 3, these inputs on the multiplexers are denoted by S and G). The outputs of the multiplexers 621,622, 623, 624 are one of the inputs of the 631, 632, 633, 634 EXCLUSIVE OR gates, the other of the 631, 632, 633, 634 CLOSE or OR gates 6v7, 6v8, 6v9, 6v10 is the input of the step 4 circuit. to its outputs, the 6k 1.6k2.6k3, 6k4 outputs of the 631, 632, 633, 634 EXCLUSIVE OR gates are connected to the 3 D / A converter input. The operation of the 6 logical networks is as follows:

From the output of the 4-bit counter 2, the weighted 1-2-4-8 signals are input as input signals to one of the two inputs 6bl, 6b2, 6b3, 6b4 of the two gate 611, 612, 613, 614 and the other 6vl, 6v2, 6v3, 6v4 Depending on the state of the control signals arriving at its input, they either reach the 6 * 1,622,623, 624 multiplexers. The 621,622,623,624 multiplexers switch one of the two input signals to the output signal.

189,346 lighter depending on the state of the control signal being output to the 6v5 input. In one state of the control signal, signals corresponding to weights 1-2-4-8 are coupled to the outputs of the multiplexers 621,622, 623, 624. The control signal arriving at the blocking 6v6 input is used to disable the multiplexers 621,622, 623,624. The signals from the outputs of the multiplexers 621,622, 623, 624 are fed to one of the inputs 631, 632, 633, 634, which are outputs 6kl, 6k2, 6k3,6k4 depending on the status of the other inputs 6v7, 6v8, 6v9, 6v10. or signals appearing at one of the inputs of the 631,632,633,634 EXCLUSIVE OR gates or inverted.

The object of the present invention has achieved its object and thus has the following advantages over known prior art solutions:

- enables the creation of a versatile multifunctional step signal generator whose output signal can be modified by a built-in program or by external control,

- the output signal is free of false impulses,

- there is no need to stop the counter properly,

- the counter gate of the counter is released,

- in the operation of the step signal generator, the waveforms are formed by static signals.

Claims (2)

Claims i. Modifiable multifunctional step signal generator comprising a clock generator (1) having an output (11) connected to the clock input (20) of a counter (2), an n-bit D / A converter (3) with an analog output (30), a step control circuit (4) with control outputs (4l ... 4m), further comprising a logic network (6) having signal inputs (6bl ... 6bn) to the outputs (21 ... 2n) of the counter (2), control input (6vl) , .. 6vm) is connected to the output (4l ... 4m) of the step control circuit (4), its signal outputs (6kl ... 6kn) are connected to the input (31 ... 3n) of the D / A converter (3). Second step signal generator according to claim 1 ¹ characterized in that the logic network (6) comprises four two-input AND gate (6ll, 612, 613, 614) having one input (6b 1, 6b2, 6B3, 6b4) 4 bit to the outputs of the counter (2), the other input (6vl, 6v2, 6v3, 6v4) up to the step control current to the outputs of the circuit (4), the output of the lower AND gate (6ll) to one input of the first multiplexer (621), the second AND gate output to the second input of the first multiplexer (621) and to the input of the second multiplexer (622), output of the third AND gate (613) to the other input of the second multiplexer (622) and to the fourth input of the third The output of (614) is connected to the second input of the third multiplexer (623) and one of the inputs of the fourth multiplexer (624), the other input of the fourth multiplexer (624) is connected to the top, to the signal select input (6v5) and (6v6) the price of the stair controller the outputs of the circuit (4) are connected, the outputs of the multiplexers (621, 622, 623, 624) to one of the inputs of the EXCLUSIVE OR gates (631, 632, 633, 634), the EXCLUSIVE OR gates (31, 632, 633, 634) ) to the outputs of another input (4), the output (6kl, 6k2, 6k3, 6k4) of the EXCLUSIVE OR gates (631, 632, 633, 634) D / A converter (3) is connected to input.