HK48494A - Apparatus for accelerating store operations in a RISC computer - Google Patents

Apparatus for accelerating store operations in a RISC computer

Info

Publication number
HK48494A
HK48494A HK48494A HK48494A HK48494A HK 48494 A HK48494 A HK 48494A HK 48494 A HK48494 A HK 48494A HK 48494 A HK48494 A HK 48494A HK 48494 A HK48494 A HK 48494A
Authority
HK
Hong Kong
Prior art keywords
accelerating
store operations
risc computer
risc
computer
Prior art date
Application number
HK48494A
Other languages
English (en)
Inventor
Eric Hartwig Jensen
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of HK48494A publication Critical patent/HK48494A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Information Transfer Systems (AREA)
HK48494A 1989-12-29 1994-05-19 Apparatus for accelerating store operations in a RISC computer HK48494A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US45857689A 1989-12-29 1989-12-29

Publications (1)

Publication Number Publication Date
HK48494A true HK48494A (en) 1994-05-27

Family

ID=23821316

Family Applications (1)

Application Number Title Priority Date Filing Date
HK48494A HK48494A (en) 1989-12-29 1994-05-19 Apparatus for accelerating store operations in a RISC computer

Country Status (6)

Country Link
US (1) US5293499A (fr)
JP (1) JP2916605B2 (fr)
AU (1) AU629007B2 (fr)
CA (1) CA2026225C (fr)
GB (1) GB2239535B (fr)
HK (1) HK48494A (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2539974B2 (ja) * 1991-11-20 1996-10-02 富士通株式会社 情報処理装置におけるレジスタの読出制御方式
US5928357A (en) * 1994-09-15 1999-07-27 Intel Corporation Circuitry and method for performing branching without pipeline delay
US5644742A (en) * 1995-02-14 1997-07-01 Hal Computer Systems, Inc. Processor structure and method for a time-out checkpoint
US6862677B1 (en) 2000-02-16 2005-03-01 Koninklijke Philips Electronics N.V. System and method for eliminating write back to register using dead field indicator
US6851044B1 (en) 2000-02-16 2005-02-01 Koninklijke Philips Electronics N.V. System and method for eliminating write backs with buffer for exception processing
US20060179265A1 (en) * 2005-02-08 2006-08-10 Flood Rachel M Systems and methods for executing x-form instructions
CN102779023A (zh) * 2011-05-12 2012-11-14 中兴通讯股份有限公司 一种处理器的环回结构及数据环回处理方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1443777A (en) * 1973-07-19 1976-07-28 Int Computers Ltd Data processing apparatus
JPS6028015B2 (ja) * 1980-08-28 1985-07-02 日本電気株式会社 情報処理装置
US4402042A (en) * 1980-11-24 1983-08-30 Texas Instruments Incorporated Microprocessor system with instruction pre-fetch
JPS592143A (ja) * 1982-06-29 1984-01-07 Hitachi Ltd 情報処理装置
US4685058A (en) * 1983-08-29 1987-08-04 Amdahl Corporation Two-stage pipelined execution unit and control stores
ATE24784T1 (de) * 1983-09-16 1987-01-15 Ibm Einrichtung im befehlswerk eines fliessbandprozessors zur befehlsunterbrechung und -wiederholung.
US4734852A (en) * 1985-08-30 1988-03-29 Advanced Micro Devices, Inc. Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor
US4766566A (en) * 1986-08-18 1988-08-23 International Business Machines Corp. Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing
US5185870A (en) * 1987-04-10 1993-02-09 Tandem Computers, Inc, System to determine if modification of first macroinstruction to execute in fewer clock cycles
CA1327080C (fr) * 1987-05-26 1994-02-15 Yoshiko Yamaguchi Microprocesseur pour ordinateur a jeu d'instructions reduit
US5136696A (en) * 1988-06-27 1992-08-04 Prime Computer, Inc. High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions
JP2858140B2 (ja) * 1988-10-19 1999-02-17 アポロ・コンピューター・インコーポレーテッド パイプラインプロセッサ装置および方法
US5088035A (en) * 1988-12-09 1992-02-11 Commodore Business Machines, Inc. System for accelerating execution of program instructions by a microprocessor

Also Published As

Publication number Publication date
CA2026225A1 (fr) 1991-06-30
JP2916605B2 (ja) 1999-07-05
JPH03204030A (ja) 1991-09-05
GB2239535B (en) 1993-08-25
AU5874790A (en) 1991-07-04
CA2026225C (fr) 1995-05-23
AU629007B2 (en) 1992-09-24
US5293499A (en) 1994-03-08
GB2239535A (en) 1991-07-03
GB9016459D0 (en) 1990-09-12

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)