HK1080215A1 - Foldable substrate with ground plane having a particular shape and corresponding manufacturing method - Google Patents

Foldable substrate with ground plane having a particular shape and corresponding manufacturing method

Info

Publication number
HK1080215A1
HK1080215A1 HK06102862.5A HK06102862A HK1080215A1 HK 1080215 A1 HK1080215 A1 HK 1080215A1 HK 06102862 A HK06102862 A HK 06102862A HK 1080215 A1 HK1080215 A1 HK 1080215A1
Authority
HK
Hong Kong
Prior art keywords
ground plane
particular shape
corresponding manufacturing
foldable substrate
foldable
Prior art date
Application number
HK06102862.5A
Other languages
English (en)
Chinese (zh)
Inventor
Geoffery Reid
Edward Jaeck
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1080215A1 publication Critical patent/HK1080215A1/xx

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/093—Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
HK06102862.5A 2003-06-02 2006-03-06 Foldable substrate with ground plane having a particular shape and corresponding manufacturing method HK1080215A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/452,873 US7057116B2 (en) 2003-06-02 2003-06-02 Selective reference plane bridge(s) on folded package
PCT/US2004/016006 WO2004109774A2 (fr) 2003-06-02 2004-05-21 Pont(s) reliant des plans de reference selectifs sur un boitier replie

Publications (1)

Publication Number Publication Date
HK1080215A1 true HK1080215A1 (en) 2006-04-21

Family

ID=33452083

Family Applications (1)

Application Number Title Priority Date Filing Date
HK06102862.5A HK1080215A1 (en) 2003-06-02 2006-03-06 Foldable substrate with ground plane having a particular shape and corresponding manufacturing method

Country Status (6)

Country Link
US (1) US7057116B2 (fr)
EP (1) EP1629534B1 (fr)
CN (1) CN100583428C (fr)
HK (1) HK1080215A1 (fr)
TW (1) TWI243465B (fr)
WO (1) WO2004109774A2 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7071420B2 (en) * 2002-12-18 2006-07-04 Micron Technology, Inc. Methods and apparatus for a flexible circuit interposer
ES2336575T3 (es) 2005-09-22 2010-04-14 Biocompatibles Uk Limited Polipeptidos de fusion glp-1 (peptido-1 similar al glucagon) con resistencia aumentada a la peptidasa.
US7816778B2 (en) * 2007-02-20 2010-10-19 Micron Technology, Inc. Packaged IC device comprising an embedded flex circuit on leadframe, and methods of making same
US7955954B2 (en) 2008-04-14 2011-06-07 Infineon Technologies Ag Method of making semiconductor devices employing first and second carriers
US20120194990A1 (en) * 2011-01-31 2012-08-02 Martin Kuster Semiconductor Arrangements
US20130249542A1 (en) * 2012-03-21 2013-09-26 Yang Zhao Foldable substrate
CN104981102B (zh) * 2014-04-10 2018-09-18 广东丹邦科技有限公司 一种多芯片嵌入式的柔性电路板及其制造方法
CN105431292B (zh) * 2014-07-11 2018-06-08 英特尔公司 可弯曲并且可拉伸的电子器件和方法
CN104486902B (zh) * 2014-11-27 2018-01-16 深圳市华星光电技术有限公司 弯折型印刷电路板
DE102015113928A1 (de) 2015-08-21 2017-02-23 Schreiner Group Gmbh & Co. Kg Gegenstand mit einer elektronischen Einheit und mit Leiterstrukturen auf einer Trägerstruktur
US11094633B2 (en) 2016-06-30 2021-08-17 Intel Corporation Bridge die design for high bandwidth memory interface
US10733136B1 (en) * 2019-03-01 2020-08-04 Western Digital Technologies, Inc. Vertical surface mount type C USB connector

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Publication number Priority date Publication date Assignee Title
JPH02260598A (ja) 1989-03-31 1990-10-23 Nec Corp 立体配線板の製造方法
JPH0513967A (ja) 1991-07-03 1993-01-22 Mitsubishi Electric Corp 半導体記憶制御装置及びその高密度実装方法
CA2101454C (fr) * 1992-07-31 1998-09-22 Kenjiro Watanabe Tete d'ecriture a jet d'encre, cartouche et appareil connexes et methode de fabrication
US5777265A (en) * 1993-01-21 1998-07-07 Intel Corporation Multilayer molded plastic package design
US5719436A (en) * 1995-03-13 1998-02-17 Intel Corporation Package housing multiple semiconductor dies
US5936848A (en) * 1995-12-20 1999-08-10 Intel Corporation Electronics package that has a substrate with an array of hollow vias and solder balls that are eccentrically located on the vias
FR2754416B1 (fr) 1996-10-04 1998-12-18 Thomson Csf Module electronique et son procede de fabrication
US6225688B1 (en) * 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US6208521B1 (en) * 1997-05-19 2001-03-27 Nitto Denko Corporation Film carrier and laminate type mounting structure using same
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
KR100514558B1 (ko) 1998-09-09 2005-09-13 세이코 엡슨 가부시키가이샤 반도체 장치 및 그 제조방법, 회로기판 및 전자기기
US6365962B1 (en) * 2000-03-29 2002-04-02 Intel Corporation Flip-chip on flex for high performance packaging applications
US6544816B1 (en) * 1999-08-20 2003-04-08 Texas Instruments Incorporated Method of encapsulating thin semiconductor chip-scale packages
US6489557B2 (en) * 1999-08-30 2002-12-03 Intel Corporation Implementing micro BGA™ assembly techniques for small die
JP2001203319A (ja) * 2000-01-18 2001-07-27 Sony Corp 積層型半導体装置
US6444921B1 (en) * 2000-02-03 2002-09-03 Fujitsu Limited Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like
US6436318B1 (en) * 2000-03-30 2002-08-20 Intel Corporation Paper substrates for use in integrated circuit packaging molding processes
US6350633B1 (en) * 2000-08-22 2002-02-26 Charles W. C. Lin Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint
US6544813B1 (en) * 2000-10-02 2003-04-08 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6448108B1 (en) * 2000-10-02 2002-09-10 Charles W. C. Lin Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment
US6840777B2 (en) * 2000-11-30 2005-01-11 Intel Corporation Solderless electronics packaging
US6521485B2 (en) * 2001-01-17 2003-02-18 Walsin Advanced Electronics Ltd Method for manufacturing wafer level chip size package
US6664483B2 (en) * 2001-05-15 2003-12-16 Intel Corporation Electronic package with high density interconnect and associated methods
US6532162B2 (en) * 2001-05-26 2003-03-11 Intel Corporation Reference plane of integrated circuit packages
US6800947B2 (en) * 2001-06-27 2004-10-05 Intel Corporation Flexible tape electronics packaging

Also Published As

Publication number Publication date
WO2004109774A2 (fr) 2004-12-16
EP1629534B1 (fr) 2014-12-24
CN1795555A (zh) 2006-06-28
US20040238206A1 (en) 2004-12-02
EP1629534A2 (fr) 2006-03-01
WO2004109774A3 (fr) 2005-02-17
US7057116B2 (en) 2006-06-06
TW200507224A (en) 2005-02-16
CN100583428C (zh) 2010-01-20
TWI243465B (en) 2005-11-11

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20210519