HK1064463A1 - Method and apparatus for read launch optimizations in memory interconnect - Google Patents

Method and apparatus for read launch optimizations in memory interconnect

Info

Publication number
HK1064463A1
HK1064463A1 HK04107028.7A HK04107028A HK1064463A1 HK 1064463 A1 HK1064463 A1 HK 1064463A1 HK 04107028 A HK04107028 A HK 04107028A HK 1064463 A1 HK1064463 A1 HK 1064463A1
Authority
HK
Hong Kong
Prior art keywords
optimizations
read
memory interconnect
launch
read launch
Prior art date
Application number
HK04107028.7A
Other languages
English (en)
Inventor
Randy Osborne
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1064463A1 publication Critical patent/HK1064463A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
HK04107028.7A 2001-11-12 2004-09-15 Method and apparatus for read launch optimizations in memory interconnect HK1064463A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/010,994 US6941425B2 (en) 2001-11-12 2001-11-12 Method and apparatus for read launch optimizations in memory interconnect
PCT/US2002/036040 WO2003042849A2 (en) 2001-11-12 2002-11-07 Method and apparatus for read launch optimizations in memory interconnect

Publications (1)

Publication Number Publication Date
HK1064463A1 true HK1064463A1 (en) 2005-01-28

Family

ID=21748391

Family Applications (1)

Application Number Title Priority Date Filing Date
HK04107028.7A HK1064463A1 (en) 2001-11-12 2004-09-15 Method and apparatus for read launch optimizations in memory interconnect

Country Status (9)

Country Link
US (1) US6941425B2 (xx)
EP (1) EP1444588B1 (xx)
KR (1) KR100618474B1 (xx)
CN (2) CN100409211C (xx)
AT (1) ATE424582T1 (xx)
DE (1) DE60231422D1 (xx)
HK (1) HK1064463A1 (xx)
TW (1) TWI301235B (xx)
WO (1) WO2003042849A2 (xx)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7320094B2 (en) * 2003-07-22 2008-01-15 Intel Corporation Retraining derived clock receivers
US7111153B2 (en) * 2003-09-30 2006-09-19 Intel Corporation Early data return indication mechanism
US7966439B1 (en) * 2004-11-24 2011-06-21 Nvidia Corporation Apparatus, system, and method for a fast data return memory controller
US20070005868A1 (en) * 2005-06-30 2007-01-04 Osborne Randy B Method, apparatus and system for posted write buffer for memory with unidirectional full duplex interface
US8325768B2 (en) 2005-08-24 2012-12-04 Intel Corporation Interleaving data packets in a packet-based communication system
US8441913B2 (en) 2005-09-27 2013-05-14 Qualcomm Incorporated Switching diversity in broadcast OFDM systems based on multiple receive antennas
US7783823B2 (en) * 2007-07-31 2010-08-24 Hewlett-Packard Development Company, L.P. Hardware device data buffer
JP5654480B2 (ja) * 2008-12-19 2015-01-14 ヒューレット−パッカード デベロップメント カンパニー エル．ピー．Ｈｅｗｌｅｔｔ‐Ｐａｃｋａｒｄ Ｄｅｖｅｌｏｐｍｅｎｔ Ｃｏｍｐａｎｙ， Ｌ．Ｐ． 均一な読み出し待ち時間のための冗長なデータ記憶
US8839275B1 (en) 2011-06-06 2014-09-16 Proximal Data, Inc. Method for intercepting input/output requests and responses
US9442859B1 (en) 2012-06-17 2016-09-13 Samsung Electronics Co., Ltd. Method for asynchronous population of data caches used with mass storage devices
US9104552B1 (en) 2012-06-23 2015-08-11 Samsung Electronics Co., Ltd. Method for the use of shadow ghost lists to prevent excessive wear on FLASH based cache devices
US9507746B2 (en) 2012-10-22 2016-11-29 Intel Corporation Control messaging in multislot link layer flit
US9418035B2 (en) * 2012-10-22 2016-08-16 Intel Corporation High performance interconnect physical layer
CN107797759B (zh) * 2016-09-05 2021-05-18 北京忆恒创源科技有限公司 访问缓存信息的方法、装置与驱动器

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE130447T1 (de) 1990-09-27 1995-12-15 Siemens Nixdorf Inf Syst Multiprozessorsystem mit gemeinsamem speicher.
JPH07504773A (ja) 1992-03-18 1995-05-25 セイコーエプソン株式会社 マルチ幅のメモリ・サブシステムをサポートするためのシステム並びに方法
US6487626B2 (en) 1992-09-29 2002-11-26 Intel Corporaiton Method and apparatus of bus interface for a processor
JP3010947B2 (ja) 1992-11-26 2000-02-21 日本電気株式会社 メモリアクセス制御装置
US5636364A (en) 1994-12-01 1997-06-03 International Business Machines Corporation Method for enabling concurrent misses in a cache memory
US5552059A (en) * 1995-03-15 1996-09-03 Canadian Forest Products Ltd. Process to decontaminate soil containing chlorophenols
US6308248B1 (en) 1996-12-31 2001-10-23 Compaq Computer Corporation Method and system for allocating memory space using mapping controller, page table and frame numbers
FR2759178B1 (fr) * 1997-02-05 1999-04-09 Sgs Thomson Microelectronics Circuit de gestion de memoire dans un environnement multi-utilisateurs avec requete et priorite d'acces
US6092158A (en) 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams
US6285679B1 (en) 1997-08-22 2001-09-04 Avici Systems, Inc. Methods and apparatus for event-driven routing
US6247084B1 (en) 1997-10-08 2001-06-12 Lsi Logic Corporation Integrated circuit with unified memory system and dual bus architecture
US6295581B1 (en) 1998-02-20 2001-09-25 Ati Technologies, Inc. Method and apparatus for assuring cache coherency
US6266747B1 (en) * 1998-10-30 2001-07-24 Telefonaktiebolaget Lm Ericsson (Publ) Method for writing data into data storage units
JP5220974B2 (ja) * 1999-10-14 2013-06-26 ブルアーク ユーケー リミテッド ハードウェア実行又はオペレーティングシステム機能の加速のための装置及び方法

Also Published As

Publication number Publication date
ATE424582T1 (de) 2009-03-15
CN1908924A (zh) 2007-02-07
WO2003042849A2 (en) 2003-05-22
US20030093631A1 (en) 2003-05-15
DE60231422D1 (de) 2009-04-16
KR100618474B1 (ko) 2006-08-31
EP1444588B1 (en) 2009-03-04
WO2003042849A3 (en) 2003-10-16
TWI301235B (en) 2008-09-21
US6941425B2 (en) 2005-09-06
CN1585934A (zh) 2005-02-23
KR20050056934A (ko) 2005-06-16
EP1444588A2 (en) 2004-08-11
CN100409211C (zh) 2008-08-06

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20121107