HK1030998A1 - Method and apparatus for correcting a multilevel cell memory by using interleaving - Google Patents

Method and apparatus for correcting a multilevel cell memory by using interleaving

Info

Publication number
HK1030998A1
HK1030998A1 HK01100356A HK01100356A HK1030998A1 HK 1030998 A1 HK1030998 A1 HK 1030998A1 HK 01100356 A HK01100356 A HK 01100356A HK 01100356 A HK01100356 A HK 01100356A HK 1030998 A1 HK1030998 A1 HK 1030998A1
Authority
HK
Hong Kong
Prior art keywords
interleaving
correcting
cell memory
multilevel cell
multilevel
Prior art date
Application number
HK01100356A
Other languages
English (en)
Inventor
Mark J Christopherson
Mark E Bauer
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK1030998A1 publication Critical patent/HK1030998A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
HK01100356A 1996-09-06 2001-01-12 Method and apparatus for correcting a multilevel cell memory by using interleaving HK1030998A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/708,212 US5754566A (en) 1996-09-06 1996-09-06 Method and apparatus for correcting a multilevel cell memory by using interleaving
PCT/US1997/015607 WO1998010425A1 (fr) 1996-09-06 1997-09-05 Procede et appareil servant a corriger la memoire de cellules multiniveau a l'aide de l'entrelacement

Publications (1)

Publication Number Publication Date
HK1030998A1 true HK1030998A1 (en) 2001-05-25

Family

ID=24844844

Family Applications (1)

Application Number Title Priority Date Filing Date
HK01100356A HK1030998A1 (en) 1996-09-06 2001-01-12 Method and apparatus for correcting a multilevel cell memory by using interleaving

Country Status (9)

Country Link
US (1) US5754566A (fr)
EP (1) EP1019821B1 (fr)
KR (1) KR100327883B1 (fr)
CN (1) CN1161791C (fr)
AU (1) AU4251697A (fr)
DE (1) DE69721076T2 (fr)
HK (1) HK1030998A1 (fr)
TW (1) TW364111B (fr)
WO (1) WO1998010425A1 (fr)

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US6857099B1 (en) * 1996-09-18 2005-02-15 Nippon Steel Corporation Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
US5754567A (en) * 1996-10-15 1998-05-19 Micron Quantum Devices, Inc. Write reduction in flash memory systems through ECC usage
US6269403B1 (en) * 1997-06-30 2001-07-31 Microsoft Corporation Browser and publisher for multimedia object storage, retrieval and transfer
US6604144B1 (en) 1997-06-30 2003-08-05 Microsoft Corporation Data format for multimedia object storage, retrieval and transfer
JP3165101B2 (ja) * 1998-03-05 2001-05-14 日本電気アイシーマイコンシステム株式会社 多値式半導体メモリ装置およびその不良救済方法
DE69907622T2 (de) 1999-02-10 2004-03-25 Stmicroelectronics S.R.L., Agrate Brianza Verfahren zur Fehlerkorrektur in einem in einer Mehrpegelspeicherzelle gespeicherten Binärwort, mit einer Minimumanzahl von Korrekturbits
JP4074029B2 (ja) * 1999-06-28 2008-04-09 株式会社東芝 フラッシュメモリ
US6487685B1 (en) * 1999-09-30 2002-11-26 Silicon Graphics, Inc. System and method for minimizing error correction code bits in variable sized data formats
IT1321049B1 (it) * 2000-11-07 2003-12-30 St Microelectronics Srl Metodo di costruzione di un codice a controllo dell'errore polivalenteper celle di memoria multilivello funzionanti a un numero variabile di
ITTO20010529A1 (it) * 2001-06-01 2002-12-01 St Microelectronics Srl Metodo di controllo dell'errore in celle di memoria multilivello con numero di bit memorizzati configurabile.
US6483743B1 (en) * 2001-06-18 2002-11-19 Intel Corporation Multilevel cell memory architecture
JP4437519B2 (ja) * 2001-08-23 2010-03-24 スパンション エルエルシー 多値セルメモリ用のメモリコントローラ
JP4856848B2 (ja) 2001-10-11 2012-01-18 アルテラ コーポレイション プログラマブルロジックリソース上のエラー検出
ITMI20022634A1 (it) * 2002-12-13 2004-06-14 St Microelectronics Srl Dispositivo elettronico integrato e metodo
ITMI20022669A1 (it) * 2002-12-18 2004-06-19 Simicroelectronics S R L Struttura e metodo di rilevamento errori in un dispositivo
TWI309776B (en) * 2003-10-24 2009-05-11 Hon Hai Prec Ind Co Ltd Secure storage system and method for solid memory
CN100468367C (zh) * 2003-10-29 2009-03-11 鸿富锦精密工业（深圳）有限公司 固态存储器的安全存储系统及方法
US7328377B1 (en) 2004-01-27 2008-02-05 Altera Corporation Error correction for programmable logic integrated circuits
US7409623B2 (en) * 2004-11-04 2008-08-05 Sigmatel, Inc. System and method of reading non-volatile computer memory
US7447948B2 (en) * 2005-11-21 2008-11-04 Intel Corporation ECC coding for high speed implementation
US7568135B2 (en) 2006-05-15 2009-07-28 Apple Inc. Use of alternative value in cell detection
US7639531B2 (en) 2006-05-15 2009-12-29 Apple Inc. Dynamic cell bit resolution
US7613043B2 (en) 2006-05-15 2009-11-03 Apple Inc. Shifting reference values to account for voltage sag
US7639542B2 (en) 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
US7701797B2 (en) 2006-05-15 2010-04-20 Apple Inc. Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
US7852690B2 (en) 2006-05-15 2010-12-14 Apple Inc. Multi-chip package for a flash memory
US8000134B2 (en) 2006-05-15 2011-08-16 Apple Inc. Off-die charge pump that supplies multiple flash devices
US7551486B2 (en) 2006-05-15 2009-06-23 Apple Inc. Iterative memory cell charging based on reference cell value
US7511646B2 (en) 2006-05-15 2009-03-31 Apple Inc. Use of 8-bit or higher A/D for NAND cell value
KR100845529B1 (ko) 2007-01-03 2008-07-10 삼성전자주식회사 플래시 메모리 장치의 이씨씨 제어기 및 그것을 포함한메모리 시스템
US7492287B2 (en) * 2007-05-23 2009-02-17 Micron Technology, Inc. Two-bit tri-level forced transition encoding
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KR101403314B1 (ko) 2008-05-23 2014-06-05 삼성전자주식회사 메모리 장치 및 데이터 비트 저장 방법
US8583986B2 (en) * 2008-12-17 2013-11-12 Seagate Technology Llc Solid-state memory with error correction coding
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KR101623730B1 (ko) * 2009-11-23 2016-05-25 삼성전자주식회사 인터리버 장치
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Also Published As

Publication number Publication date
CN1235691A (zh) 1999-11-17
DE69721076D1 (de) 2003-05-22
EP1019821B1 (fr) 2003-04-16
TW364111B (en) 1999-07-11
KR100327883B1 (ko) 2002-05-22
US5754566A (en) 1998-05-19
WO1998010425A1 (fr) 1998-03-12
KR20000068504A (ko) 2000-11-25
EP1019821A1 (fr) 2000-07-19
CN1161791C (zh) 2004-08-11
DE69721076T2 (de) 2003-11-06
AU4251697A (en) 1998-03-26
EP1019821A4 (fr) 2000-07-19

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20100905