DE69721076T2 - Verfahren und vorrichtung zur korrektur von mehrpegel-speicherzellenanordungen unter verwendung von verschachtelung - Google Patents

Verfahren und vorrichtung zur korrektur von mehrpegel-speicherzellenanordungen unter verwendung von verschachtelung

Info

Publication number
DE69721076T2
DE69721076T2 DE69721076T DE69721076T DE69721076T2 DE 69721076 T2 DE69721076 T2 DE 69721076T2 DE 69721076 T DE69721076 T DE 69721076T DE 69721076 T DE69721076 T DE 69721076T DE 69721076 T2 DE69721076 T2 DE 69721076T2
Authority
DE
Germany
Prior art keywords
nestling
storage cell
level storage
cell arrangements
correcting multi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69721076T
Other languages
English (en)
Other versions
DE69721076D1 (de
Inventor
J Christopherson
E Bauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE69721076D1 publication Critical patent/DE69721076D1/de
Publication of DE69721076T2 publication Critical patent/DE69721076T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
DE69721076T 1996-09-06 1997-09-05 Verfahren und vorrichtung zur korrektur von mehrpegel-speicherzellenanordungen unter verwendung von verschachtelung Expired - Lifetime DE69721076T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/708,212 US5754566A (en) 1996-09-06 1996-09-06 Method and apparatus for correcting a multilevel cell memory by using interleaving
PCT/US1997/015607 WO1998010425A1 (en) 1996-09-06 1997-09-05 Method and apparatus for correcting a multilevel cell memory by using interleaving

Publications (2)

Publication Number Publication Date
DE69721076D1 DE69721076D1 (de) 2003-05-22
DE69721076T2 true DE69721076T2 (de) 2003-11-06

Family

ID=24844844

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69721076T Expired - Lifetime DE69721076T2 (de) 1996-09-06 1997-09-05 Verfahren und vorrichtung zur korrektur von mehrpegel-speicherzellenanordungen unter verwendung von verschachtelung

Country Status (9)

Country Link
US (1) US5754566A (de)
EP (1) EP1019821B1 (de)
KR (1) KR100327883B1 (de)
CN (1) CN1161791C (de)
AU (1) AU4251697A (de)
DE (1) DE69721076T2 (de)
HK (1) HK1030998A1 (de)
TW (1) TW364111B (de)
WO (1) WO1998010425A1 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6002614A (en) 1991-02-08 1999-12-14 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US6353554B1 (en) 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US5787484A (en) 1996-08-08 1998-07-28 Micron Technology, Inc. System and method which compares data preread from memory cells to data to be written to the cells
US6857099B1 (en) * 1996-09-18 2005-02-15 Nippon Steel Corporation Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
US5754567A (en) * 1996-10-15 1998-05-19 Micron Quantum Devices, Inc. Write reduction in flash memory systems through ECC usage
US6604144B1 (en) 1997-06-30 2003-08-05 Microsoft Corporation Data format for multimedia object storage, retrieval and transfer
US6269403B1 (en) * 1997-06-30 2001-07-31 Microsoft Corporation Browser and publisher for multimedia object storage, retrieval and transfer
JP3165101B2 (ja) * 1998-03-05 2001-05-14 日本電気アイシーマイコンシステム株式会社 多値式半導体メモリ装置およびその不良救済方法
EP1028379B1 (de) 1999-02-10 2003-05-07 STMicroelectronics S.r.l. Verfahren zur Fehlerkorrektur in einem in einer Mehrpegelspeicherzelle gespeicherten Binärwort, mit einer Minimumanzahl von Korrekturbits
JP4074029B2 (ja) 1999-06-28 2008-04-09 株式会社東芝 フラッシュメモリ
US6487685B1 (en) * 1999-09-30 2002-11-26 Silicon Graphics, Inc. System and method for minimizing error correction code bits in variable sized data formats
IT1321049B1 (it) * 2000-11-07 2003-12-30 St Microelectronics Srl Metodo di costruzione di un codice a controllo dell'errore polivalenteper celle di memoria multilivello funzionanti a un numero variabile di
ITTO20010529A1 (it) * 2001-06-01 2002-12-01 St Microelectronics Srl Metodo di controllo dell'errore in celle di memoria multilivello con numero di bit memorizzati configurabile.
US6483743B1 (en) * 2001-06-18 2002-11-19 Intel Corporation Multilevel cell memory architecture
JP4437519B2 (ja) * 2001-08-23 2010-03-24 スパンション エルエルシー 多値セルメモリ用のメモリコントローラ
US7310757B2 (en) * 2001-10-11 2007-12-18 Altera Corporation Error detection on programmable logic resources
ITMI20022634A1 (it) * 2002-12-13 2004-06-14 St Microelectronics Srl Dispositivo elettronico integrato e metodo
ITMI20022669A1 (it) * 2002-12-18 2004-06-19 Simicroelectronics S R L Struttura e metodo di rilevamento errori in un dispositivo
TWI309776B (en) * 2003-10-24 2009-05-11 Hon Hai Prec Ind Co Ltd Secure storage system and method for solid memory
CN100468367C (zh) * 2003-10-29 2009-03-11 鸿富锦精密工业（深圳）有限公司 固态存储器的安全存储系统及方法
US7328377B1 (en) 2004-01-27 2008-02-05 Altera Corporation Error correction for programmable logic integrated circuits
US7409623B2 (en) * 2004-11-04 2008-08-05 Sigmatel, Inc. System and method of reading non-volatile computer memory
US7447948B2 (en) * 2005-11-21 2008-11-04 Intel Corporation ECC coding for high speed implementation
US7639542B2 (en) 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
US7852690B2 (en) 2006-05-15 2010-12-14 Apple Inc. Multi-chip package for a flash memory
US7701797B2 (en) 2006-05-15 2010-04-20 Apple Inc. Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
US7568135B2 (en) * 2006-05-15 2009-07-28 Apple Inc. Use of alternative value in cell detection
US7511646B2 (en) 2006-05-15 2009-03-31 Apple Inc. Use of 8-bit or higher A/D for NAND cell value
US7639531B2 (en) 2006-05-15 2009-12-29 Apple Inc. Dynamic cell bit resolution
US7551486B2 (en) 2006-05-15 2009-06-23 Apple Inc. Iterative memory cell charging based on reference cell value
US8000134B2 (en) 2006-05-15 2011-08-16 Apple Inc. Off-die charge pump that supplies multiple flash devices
US7613043B2 (en) 2006-05-15 2009-11-03 Apple Inc. Shifting reference values to account for voltage sag
KR100845529B1 (ko) 2007-01-03 2008-07-10 삼성전자주식회사 플래시 메모리 장치의 이씨씨 제어기 및 그것을 포함한메모리 시스템
US7492287B2 (en) * 2007-05-23 2009-02-17 Micron Technology, Inc. Two-bit tri-level forced transition encoding
KR101506655B1 (ko) * 2008-05-15 2015-03-30 삼성전자주식회사 메모리 장치 및 메모리 데이터 오류 관리 방법
KR101403314B1 (ko) 2008-05-23 2014-06-05 삼성전자주식회사 메모리 장치 및 데이터 비트 저장 방법
US8583986B2 (en) * 2008-12-17 2013-11-12 Seagate Technology Llc Solid-state memory with error correction coding
KR101616100B1 (ko) * 2009-09-25 2016-04-28 삼성전자주식회사 메모리 시스템 및 그것의 동작 방법
KR101623730B1 (ko) * 2009-11-23 2016-05-25 삼성전자주식회사 인터리버 장치
US9195540B2 (en) * 2010-10-06 2015-11-24 HGST, Inc. Multiple sector parallel access memory array with error correction
US8972821B2 (en) * 2010-12-23 2015-03-03 Texas Instruments Incorporated Encode and multiplex, register, and decode and error correction circuitry
US11221950B2 (en) 2019-12-19 2022-01-11 Western Digital Technologies, Inc. Storage system and method for interleaving data for enhanced quality of service
US11150839B2 (en) 2019-12-19 2021-10-19 Western Digital Technologies, Inc. Host and method for interleaving data in a storage system for enhanced quality of service

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0148488B1 (de) * 1983-12-23 1992-03-18 Hitachi, Ltd. Halbleiterspeicher mit einer Speicherstruktur mit vielfachen Pegeln
US5095344A (en) * 1988-06-08 1992-03-10 Eliyahou Harari Highly compact eprom and flash eeprom devices
CA2019351A1 (en) * 1989-07-06 1991-01-06 Francis H. Reiff Fault tolerant memory
US5450363A (en) * 1994-06-02 1995-09-12 Intel Corporation Gray coding for a multilevel cell memory system
US5475693A (en) * 1994-12-27 1995-12-12 Intel Corporation Error management processes for flash EEPROM memory arrays

Also Published As

Publication number Publication date
AU4251697A (en) 1998-03-26
KR20000068504A (ko) 2000-11-25
EP1019821A1 (de) 2000-07-19
EP1019821A4 (de) 2000-07-19
US5754566A (en) 1998-05-19
TW364111B (en) 1999-07-11
WO1998010425A1 (en) 1998-03-12
HK1030998A1 (en) 2001-05-25
KR100327883B1 (ko) 2002-05-22
CN1235691A (zh) 1999-11-17
DE69721076D1 (de) 2003-05-22
CN1161791C (zh) 2004-08-11
EP1019821B1 (de) 2003-04-16

Similar Documents

Publication Publication Date Title
DE69721076T2 (de) Verfahren und vorrichtung zur korrektur von mehrpegel-speicherzellenanordungen unter verwendung von verschachtelung
DE69723753D1 (de) Verfahren und Vorrichtung zur Reformierung von Brennstoff und Brennstoffzellensystem mit solcher Brennstoffreformierungsvorrichtung
DE69429901D1 (de) Verfahren und Vorrichtung zur Regelung von unterirdischen Speichern
DE69740113D1 (de) Vorrichtung und verfahren zur inkubation von zellen
DE69423760T2 (de) Verfahren und vorrichtung zur isolierung von mikrogefässzellen
DE69827218D1 (de) Verfahren und Vorrichtung zur Anpassung von ATM-Anpassungsschichtsformaten
DE69732447D1 (de) Verfahren und Vorrichtung zur Wiedergabe von schriftartfreien, strukturierten Dokumenten
DE69737115D1 (de) Verfahren und Vorrichtung zur Wiedergabe von schriftartfreien, strukturierten Dokumenten
DE69626977D1 (de) Gerät und verfahren zur kalibration von vielfachbehältern
DE59707814D1 (de) Verfahren und vorrichtung zur verteilung von sendungen
DE69740043D1 (de) Vorrichtung und verfahren zur erfassung von informationen unter verwendung von standardisierten objekten
DE69616153D1 (de) Verfahren und System zur automatischen Korrektur von Transkriptionen
DE69736914D1 (de) Verfahren und Vorrichtung zur Fehlerkompensation sowie ein Fehlerkompensationsprogramm speicherndes Speichermedium
DE69917270D1 (de) Verfahren und vorrichtung zur regelung von kommunikationssystemkapazität
DE59704406D1 (de) Verfahren zur temperierung von vorformlingen sowie vorrichtung zur temperierung
DE69824991D1 (de) Vorrichtung zur Herstellung von Verpackungsbehältern und Verfahren zu deren Herstellung
DE69421370T2 (de) Verfahren und Vorrichtung zur Datenspeicherung
DE69824666D1 (de) Vorrichtung zur Herstellung von Verpackungsbehältern und Verfahren zu deren Herstellung-I
DE68919256D1 (de) Verfahren und Vorrichtung zur Ermittlung von Zelleigenschaften.
DE69727046D1 (de) Verfahren, vorrichtung und system zur erzeugung von segmentzeitspannen in einem text-zu-sprache system
DE69716159D1 (de) Verfahren und Vorrichtung zur Kompensation von Sprachsignalen
DE69527707D1 (de) Verfahren unter verwendung von fluidisierten feststoffen und vorrichtung zur durchführung solcher verfahren
DE69728229D1 (de) Verfahren und Vorrichtung zur Kodierung von Tropfengewicht
DE69608301T2 (de) Verfahren zur co-produktion von amoniak und methanol
DE59708489D1 (de) Vorrichtung und Verfahren zur Durchführung von qualitätsmanagement

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: HEYER, V., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 806