HK1018166A1 - System and method for synchronization in split-level data cache system - Google Patents

System and method for synchronization in split-level data cache system

Info

Publication number
HK1018166A1
HK1018166A1 HK98114540A HK98114540A HK1018166A1 HK 1018166 A1 HK1018166 A1 HK 1018166A1 HK 98114540 A HK98114540 A HK 98114540A HK 98114540 A HK98114540 A HK 98114540A HK 1018166 A1 HK1018166 A1 HK 1018166A1
Authority
HK
Hong Kong
Prior art keywords
synchronization
split
level data
data cache
cache system
Prior art date
Application number
HK98114540A
Other languages
English (en)
Inventor
John Brennan
Peter Yan-Tek Hsu
William A Huffman
Joseph T Scanlon
Steve Scavaglia
Original Assignee
Tokyo Shibaura Electric Co Mips Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Mips Tech Inc filed Critical Tokyo Shibaura Electric Co Mips Tech Inc
Publication of HK1018166A1 publication Critical patent/HK1018166A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
HK98114540A 1993-12-15 1998-12-22 System and method for synchronization in split-level data cache system HK1018166A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/167,005 US5572704A (en) 1993-12-15 1993-12-15 System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes
PCT/JP1994/002111 WO1995016959A1 (fr) 1993-12-15 1994-12-15 Dispositif et procede de synchronisation des systemes a antememoire de donnees a plusieurs niveaux

Publications (1)

Publication Number Publication Date
HK1018166A1 true HK1018166A1 (en) 1999-12-10

Family

ID=22605558

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98114540A HK1018166A1 (en) 1993-12-15 1998-12-22 System and method for synchronization in split-level data cache system

Country Status (10)

Country Link
US (2) US5572704A (de)
EP (1) EP0684561B1 (de)
JP (1) JP2631037B2 (de)
KR (1) KR0182344B1 (de)
CN (1) CN1054223C (de)
DE (1) DE69434728T2 (de)
HK (1) HK1018166A1 (de)
SG (1) SG75776A1 (de)
TW (1) TW367441B (de)
WO (1) WO1995016959A1 (de)

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US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
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US6591361B1 (en) 1999-12-28 2003-07-08 International Business Machines Corporation Method and apparatus for converting data into different ordinal types
US6859862B1 (en) 2000-04-07 2005-02-22 Nintendo Co., Ltd. Method and apparatus for software management of on-chip cache
US6701424B1 (en) * 2000-04-07 2004-03-02 Nintendo Co., Ltd. Method and apparatus for efficient loading and storing of vectors
US6857061B1 (en) * 2000-04-07 2005-02-15 Nintendo Co., Ltd. Method and apparatus for obtaining a scalar value directly from a vector register
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US7406554B1 (en) * 2000-07-20 2008-07-29 Silicon Graphics, Inc. Queue circuit and method for memory arbitration employing same
US7185183B1 (en) 2001-08-02 2007-02-27 Mips Technologies, Inc. Atomic update of CPO state
US7181600B1 (en) 2001-08-02 2007-02-20 Mips Technologies, Inc. Read-only access to CPO registers
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US7634638B1 (en) * 2002-10-22 2009-12-15 Mips Technologies, Inc. Instruction encoding for system register bit set and clear
US6836833B1 (en) * 2002-10-22 2004-12-28 Mips Technologies, Inc. Apparatus and method for discovering a scratch pad memory configuration
JP3855270B2 (ja) * 2003-05-29 2006-12-06 ソニー株式会社 アンテナ実装方法
CN100461142C (zh) * 2005-07-05 2009-02-11 威盛电子股份有限公司 微处理器、处理器总线系统、及执行稀疏写入处理的方法
US7454492B2 (en) * 2005-08-26 2008-11-18 International Business Machines Corporation Method and apparatus for configuring and modeling server information in an enterprise tooling environment
US7596661B2 (en) * 2005-09-01 2009-09-29 Mediatek Inc. Processing modules with multilevel cache architecture
US7734901B2 (en) * 2005-10-31 2010-06-08 Mips Technologies, Inc. Processor core and method for managing program counter redirection in an out-of-order processor pipeline
US7711934B2 (en) * 2005-10-31 2010-05-04 Mips Technologies, Inc. Processor core and method for managing branch misprediction in an out-of-order processor pipeline
US7721071B2 (en) * 2006-02-28 2010-05-18 Mips Technologies, Inc. System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor
US20070204139A1 (en) 2006-02-28 2007-08-30 Mips Technologies, Inc. Compact linked-list-based multi-threaded instruction graduation buffer
US7370178B1 (en) * 2006-07-14 2008-05-06 Mips Technologies, Inc. Method for latest producer tracking in an out-of-order processor, and applications thereof
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US8032734B2 (en) * 2006-09-06 2011-10-04 Mips Technologies, Inc. Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor
US7647475B2 (en) * 2006-09-06 2010-01-12 Mips Technologies, Inc. System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue
US8078846B2 (en) 2006-09-29 2011-12-13 Mips Technologies, Inc. Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated
US9946547B2 (en) * 2006-09-29 2018-04-17 Arm Finance Overseas Limited Load/store unit for a processor, and applications thereof
US20080082793A1 (en) * 2006-09-29 2008-04-03 Mips Technologies, Inc. Detection and prevention of write-after-write hazards, and applications thereof
US7594079B2 (en) 2006-09-29 2009-09-22 Mips Technologies, Inc. Data cache virtual hint way prediction, and applications thereof
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US7769958B2 (en) * 2007-06-22 2010-08-03 Mips Technologies, Inc. Avoiding livelock using intervention messages in multiple core processors
US7953932B2 (en) * 2008-02-13 2011-05-31 International Business Machines Corporation System and method for avoiding deadlocks when performing storage updates in a multi-processor environment
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JP6093322B2 (ja) * 2014-03-18 2017-03-08 株式会社東芝 キャッシュメモリおよびプロセッサシステム
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Also Published As

Publication number Publication date
TW367441B (en) 1999-08-21
DE69434728D1 (de) 2006-06-14
DE69434728T2 (de) 2007-04-26
SG75776A1 (en) 2000-10-24
CN1054223C (zh) 2000-07-05
EP0684561B1 (de) 2006-05-10
US5572704A (en) 1996-11-05
WO1995016959A1 (fr) 1995-06-22
EP0684561A1 (de) 1995-11-29
KR960701403A (ko) 1996-02-24
US5632025A (en) 1997-05-20
CN1117767A (zh) 1996-02-28
JP2631037B2 (ja) 1997-07-16
EP0684561A4 (de) 1999-11-17
KR0182344B1 (ko) 1999-05-15

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PE Patent expired

Effective date: 20141214