HK1002779A1 - Deterministic distributed multicache coherence protocol - Google Patents

Deterministic distributed multicache coherence protocol

Info

Publication number
HK1002779A1
HK1002779A1 HK98100957A HK98100957A HK1002779A1 HK 1002779 A1 HK1002779 A1 HK 1002779A1 HK 98100957 A HK98100957 A HK 98100957A HK 98100957 A HK98100957 A HK 98100957A HK 1002779 A1 HK1002779 A1 HK 1002779A1
Authority
HK
Hong Kong
Prior art keywords
multicache
coherence protocol
deterministic distributed
deterministic
distributed
Prior art date
Application number
HK98100957A
Other languages
English (en)
Inventor
Paul N Loewenstein
Erik Hagersten
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of HK1002779A1 publication Critical patent/HK1002779A1/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
HK98100957A 1996-04-08 1998-02-09 Deterministic distributed multicache coherence protocol HK1002779A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/630,703 US5893160A (en) 1996-04-08 1996-04-08 Deterministic distributed multi-cache coherence method and system

Publications (1)

Publication Number Publication Date
HK1002779A1 true HK1002779A1 (en) 1998-09-18

Family

ID=24528258

Family Applications (1)

Application Number Title Priority Date Filing Date
HK98100957A HK1002779A1 (en) 1996-04-08 1998-02-09 Deterministic distributed multicache coherence protocol

Country Status (5)

Country Link
US (1) US5893160A (ja)
EP (1) EP0801349B1 (ja)
JP (1) JPH10105464A (ja)
DE (1) DE69721891T2 (ja)
HK (1) HK1002779A1 (ja)

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US6167490A (en) * 1996-09-20 2000-12-26 University Of Washington Using global memory information to manage memory in a computer network
US6209059B1 (en) * 1997-09-25 2001-03-27 Emc Corporation Method and apparatus for the on-line reconfiguration of the logical volumes of a data storage system
US6032217A (en) 1997-11-04 2000-02-29 Adaptec, Inc. Method for reconfiguring containers without shutting down the system and with minimal interruption to on-line processing
US6212610B1 (en) 1998-01-07 2001-04-03 Fujitsu Limited Memory protection mechanism for a distributed shared memory multiprocessor with integrated message passing support
WO1999035581A1 (en) * 1998-01-07 1999-07-15 Fujitsu Limited Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
US6209064B1 (en) 1998-01-07 2001-03-27 Fujitsu Limited Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
US6425060B1 (en) * 1999-01-05 2002-07-23 International Business Machines Corporation Circuit arrangement and method with state-based transaction scheduling
US6484240B1 (en) * 1999-07-30 2002-11-19 Sun Microsystems, Inc. Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols
US6356983B1 (en) * 2000-07-25 2002-03-12 Src Computers, Inc. System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7324995B2 (en) * 2003-11-17 2008-01-29 Rackable Systems Inc. Method for retrieving and modifying data elements on a shared medium
US20050108300A1 (en) * 2003-11-17 2005-05-19 Terrascale Technologies Inc. Method for the management of local client cache buffers in a clustered computer environment
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
US9727468B2 (en) * 2004-09-09 2017-08-08 Intel Corporation Resolving multi-core shared cache access conflicts
JP4362454B2 (ja) * 2005-04-07 2009-11-11 富士通株式会社 キャッシュコヒーレンス管理装置およびキャッシュコヒーレンス管理方法
JP4572169B2 (ja) * 2006-01-26 2010-10-27 エヌイーシーコンピュータテクノ株式会社 マルチプロセッサシステム及びその動作方法
EP1988465B1 (en) 2006-02-24 2011-11-23 Fujitsu Limited Processor, and cache control method
JP4297969B2 (ja) 2006-02-24 2009-07-15 富士通株式会社 記録制御装置および記録制御方法
JP4373485B2 (ja) * 2006-02-28 2009-11-25 富士通株式会社 情報処理装置及び該制御方法
JP4208895B2 (ja) * 2006-05-30 2009-01-14 株式会社東芝 キャッシュメモリ装置および処理方法
US7480770B2 (en) 2006-06-14 2009-01-20 Sun Microsystems, Inc. Semi-blocking deterministic directory coherence
US7574566B2 (en) * 2006-09-21 2009-08-11 Sun Microsystems, Inc. System and method for efficient software cache coherence
US7827357B2 (en) 2007-07-31 2010-11-02 Intel Corporation Providing an inclusive shared cache among multiple core-cache clusters
US8812959B2 (en) * 2009-06-30 2014-08-19 International Business Machines Corporation Method and system for delivering digital content
GB2484088B (en) * 2010-09-28 2019-08-07 Advanced Risc Mach Ltd Coherency control with writeback ordering
US8756378B2 (en) * 2011-02-17 2014-06-17 Oracle International Corporation Broadcast protocol for a network of caches
US8972663B2 (en) * 2013-03-14 2015-03-03 Oracle International Corporation Broadcast cache coherence on partially-ordered network
US10496538B2 (en) 2015-06-30 2019-12-03 Veritas Technologies Llc System, method and mechanism to efficiently coordinate cache sharing between cluster nodes operating on the same regions of a file or the file system blocks shared among multiple files
US10387314B2 (en) * 2015-08-25 2019-08-20 Oracle International Corporation Reducing cache coherence directory bandwidth by aggregating victimization requests
US10725915B1 (en) * 2017-03-31 2020-07-28 Veritas Technologies Llc Methods and systems for maintaining cache coherency between caches of nodes in a clustered environment
US10917198B2 (en) * 2018-05-03 2021-02-09 Arm Limited Transfer protocol in a data processing network
US11544193B2 (en) 2020-09-11 2023-01-03 Apple Inc. Scalable cache coherency protocol
US11934313B2 (en) 2021-08-23 2024-03-19 Apple Inc. Scalable system on a chip

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US5642494A (en) * 1994-12-21 1997-06-24 Intel Corporation Cache memory with reduced request-blocking

Also Published As

Publication number Publication date
US5893160A (en) 1999-04-06
DE69721891T2 (de) 2004-03-11
DE69721891D1 (de) 2003-06-18
EP0801349B1 (en) 2003-05-14
EP0801349A1 (en) 1997-10-15
JPH10105464A (ja) 1998-04-24

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20070325