DE69721891D1 - Deterministisches Kohärenzprotokoll für verteilten Multicache-Speicher - Google Patents

Deterministisches Kohärenzprotokoll für verteilten Multicache-Speicher

Info

Publication number
DE69721891D1
DE69721891D1 DE69721891T DE69721891T DE69721891D1 DE 69721891 D1 DE69721891 D1 DE 69721891D1 DE 69721891 T DE69721891 T DE 69721891T DE 69721891 T DE69721891 T DE 69721891T DE 69721891 D1 DE69721891 D1 DE 69721891D1
Authority
DE
Germany
Prior art keywords
multicache
deterministic
distributed
memory
coherency protocol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69721891T
Other languages
English (en)
Other versions
DE69721891T2 (de
Inventor
Paul N Loewenstein
Erik Hagersten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of DE69721891D1 publication Critical patent/DE69721891D1/de
Application granted granted Critical
Publication of DE69721891T2 publication Critical patent/DE69721891T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69721891T 1996-04-08 1997-03-25 Deterministisches Kohärenzprotokoll für verteilten Multicache-Speicher Expired - Fee Related DE69721891T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/630,703 US5893160A (en) 1996-04-08 1996-04-08 Deterministic distributed multi-cache coherence method and system
US630703 1996-04-08

Publications (2)

Publication Number Publication Date
DE69721891D1 true DE69721891D1 (de) 2003-06-18
DE69721891T2 DE69721891T2 (de) 2004-03-11

Family

ID=24528258

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69721891T Expired - Fee Related DE69721891T2 (de) 1996-04-08 1997-03-25 Deterministisches Kohärenzprotokoll für verteilten Multicache-Speicher

Country Status (5)

Country Link
US (1) US5893160A (de)
EP (1) EP0801349B1 (de)
JP (1) JPH10105464A (de)
DE (1) DE69721891T2 (de)
HK (1) HK1002779A1 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5950226A (en) * 1996-07-01 1999-09-07 Sun Microsystems, Inc. Multiprocessing system employing a three-hop communication protocol
US5860109A (en) * 1996-07-01 1999-01-12 Sun Microsystems, Inc. Methods and apparatus for a coherence transformer for connecting computer system coherence domains
US5897657A (en) * 1996-07-01 1999-04-27 Sun Microsystems, Inc. Multiprocessing system employing a coherency protocol including a reply count
US6167490A (en) * 1996-09-20 2000-12-26 University Of Washington Using global memory information to manage memory in a computer network
US6209059B1 (en) * 1997-09-25 2001-03-27 Emc Corporation Method and apparatus for the on-line reconfiguration of the logical volumes of a data storage system
US6032217A (en) * 1997-11-04 2000-02-29 Adaptec, Inc. Method for reconfiguring containers without shutting down the system and with minimal interruption to on-line processing
US6212610B1 (en) 1998-01-07 2001-04-03 Fujitsu Limited Memory protection mechanism for a distributed shared memory multiprocessor with integrated message passing support
WO1999035581A1 (en) * 1998-01-07 1999-07-15 Fujitsu Limited Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
US6209064B1 (en) 1998-01-07 2001-03-27 Fujitsu Limited Cache coherence unit with integrated message passing and memory protection for a distributed, shared memory multiprocessor system
US6425060B1 (en) * 1999-01-05 2002-07-23 International Business Machines Corporation Circuit arrangement and method with state-based transaction scheduling
US6484240B1 (en) 1999-07-30 2002-11-19 Sun Microsystems, Inc. Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols
US6356983B1 (en) * 2000-07-25 2002-03-12 Src Computers, Inc. System and method providing cache coherency and atomic memory operations in a multiprocessor computer architecture
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US20050108300A1 (en) * 2003-11-17 2005-05-19 Terrascale Technologies Inc. Method for the management of local client cache buffers in a clustered computer environment
US7324995B2 (en) * 2003-11-17 2008-01-29 Rackable Systems Inc. Method for retrieving and modifying data elements on a shared medium
US7822929B2 (en) * 2004-04-27 2010-10-26 Intel Corporation Two-hop cache coherency protocol
US9727468B2 (en) 2004-09-09 2017-08-08 Intel Corporation Resolving multi-core shared cache access conflicts
JP4362454B2 (ja) * 2005-04-07 2009-11-11 富士通株式会社 キャッシュコヒーレンス管理装置およびキャッシュコヒーレンス管理方法
JP4572169B2 (ja) * 2006-01-26 2010-10-27 エヌイーシーコンピュータテクノ株式会社 マルチプロセッサシステム及びその動作方法
WO2007096980A1 (ja) 2006-02-24 2007-08-30 Fujitsu Limited 記録制御装置および記録制御方法
JP4335300B2 (ja) 2006-02-24 2009-09-30 富士通株式会社 マルチプロセッサシステム、プロセッサ、およびキャッシュ制御方法
JP4373485B2 (ja) * 2006-02-28 2009-11-25 富士通株式会社 情報処理装置及び該制御方法
JP4208895B2 (ja) * 2006-05-30 2009-01-14 株式会社東芝 キャッシュメモリ装置および処理方法
US7480770B2 (en) 2006-06-14 2009-01-20 Sun Microsystems, Inc. Semi-blocking deterministic directory coherence
US7574566B2 (en) * 2006-09-21 2009-08-11 Sun Microsystems, Inc. System and method for efficient software cache coherence
US7827357B2 (en) 2007-07-31 2010-11-02 Intel Corporation Providing an inclusive shared cache among multiple core-cache clusters
US8812959B2 (en) * 2009-06-30 2014-08-19 International Business Machines Corporation Method and system for delivering digital content
GB2484088B (en) * 2010-09-28 2019-08-07 Advanced Risc Mach Ltd Coherency control with writeback ordering
US8756378B2 (en) * 2011-02-17 2014-06-17 Oracle International Corporation Broadcast protocol for a network of caches
US8972663B2 (en) * 2013-03-14 2015-03-03 Oracle International Corporation Broadcast cache coherence on partially-ordered network
US10496538B2 (en) 2015-06-30 2019-12-03 Veritas Technologies Llc System, method and mechanism to efficiently coordinate cache sharing between cluster nodes operating on the same regions of a file or the file system blocks shared among multiple files
US10387314B2 (en) * 2015-08-25 2019-08-20 Oracle International Corporation Reducing cache coherence directory bandwidth by aggregating victimization requests
US10725915B1 (en) 2017-03-31 2020-07-28 Veritas Technologies Llc Methods and systems for maintaining cache coherency between caches of nodes in a clustered environment
US10917198B2 (en) * 2018-05-03 2021-02-09 Arm Limited Transfer protocol in a data processing network
US11544193B2 (en) 2020-09-11 2023-01-03 Apple Inc. Scalable cache coherency protocol
US11934313B2 (en) 2021-08-23 2024-03-19 Apple Inc. Scalable system on a chip

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1239227A (en) * 1984-10-17 1988-07-12 Randy D. Pfeifer Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system
JPH0731662B2 (ja) * 1986-07-15 1995-04-10 富士通株式会社 マルチプロセッサシステム
JPH07113903B2 (ja) * 1987-06-26 1995-12-06 株式会社日立製作所 キャッシュ記憶制御方式
US5161227A (en) * 1989-11-13 1992-11-03 International Business Machines Corporation Multilevel locking system and method
US5499356A (en) * 1989-12-29 1996-03-12 Cray Research, Inc. Method and apparatus for a multiprocessor resource lockout instruction
US5301337A (en) * 1990-04-06 1994-04-05 Bolt Beranek And Newman Inc. Distributed resource management system using hashing operation to direct resource request from different processors to the processor controlling the requested resource
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5303362A (en) * 1991-03-20 1994-04-12 Digital Equipment Corporation Coupled memory multiprocessor computer system including cache coherency management protocols
US5237673A (en) * 1991-03-20 1993-08-17 Digital Equipment Corporation Memory management method for coupled memory multiprocessor systems
JPH05210640A (ja) * 1992-01-31 1993-08-20 Hitachi Ltd マルチプロセッサシステム
US5551005A (en) * 1994-02-25 1996-08-27 Intel Corporation Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches
US5572702A (en) * 1994-02-28 1996-11-05 Intel Corporation Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
US5642494A (en) * 1994-12-21 1997-06-24 Intel Corporation Cache memory with reduced request-blocking

Also Published As

Publication number Publication date
EP0801349B1 (de) 2003-05-14
EP0801349A1 (de) 1997-10-15
DE69721891T2 (de) 2004-03-11
HK1002779A1 (en) 1998-09-18
US5893160A (en) 1999-04-06
JPH10105464A (ja) 1998-04-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee