GB981780A - Improvements in digital data storage systems - Google Patents

Abstract

981,780. Digital data storage; microprogramming. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 12, 1961 [June 17, 1960], No. 21314/60. Headings G4A and G4C. On selecting an address in a storage matrix 1 of magnetic cores the next address is set up in a selection register. Register 2 selects a column of matrix 1 and the column wires are threaded through the cores of the selection register 2 so as to set the cores A 1 to A 5 to represent the column selected less one, the cores B 1 to B 8 to represent the same column, and the cores C 1 to C 8 to represent the column selected plus one, as illustrated for the fifth column. The outputs of the cores are gated by a strobe signal on line 9 to a decoder 10 which marks one out of sixteen lines. The cores in each row of the register take values according to the 1, 2, 4, 8 code. To select a column of the matrix 1, one of the transistor switches 6 is closed and a full read pulse is given to all the cores of register 2 by means of winding 4, together with a half-write pulse on winding 5a which is effective only on that row of the register associated with the closed switch 6. The effect is that two of the rows of register 2 are cleared. The pulse on winding 5a stops and a strobe pulse issues, permitting the setting of the uncleared row to be read to decoder 10 and selecting one of the column lines of matrix 1. The marking of the column line causes all three rows of the register to be set. A switch 6 is then closed, perhaps according to the information read from matrix 1, and the process repeated. The invention is applied to microprogramming in which a microinstruction contains the address of the next microinstruction.