GB9720811D0 - Dual port buffer - Google Patents

Dual port buffer

Info

Publication number
GB9720811D0
GB9720811D0 GBGB9720811.0A GB9720811A GB9720811D0 GB 9720811 D0 GB9720811 D0 GB 9720811D0 GB 9720811 A GB9720811 A GB 9720811A GB 9720811 D0 GB9720811 D0 GB 9720811D0
Authority
GB
United Kingdom
Prior art keywords
dual port
port buffer
buffer
dual
port
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
GBGB9720811.0A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Ltd
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd, SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Ltd
Priority to GBGB9720811.0A priority Critical patent/GB9720811D0/en
Publication of GB9720811D0 publication Critical patent/GB9720811D0/en
Priority to EP98307887A priority patent/EP0905610B1/en
Priority to DE69819648T priority patent/DE69819648T2/de
Priority to US09/164,227 priority patent/US6249875B1/en
Priority to JP10278224A priority patent/JPH11175313A/ja
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
GBGB9720811.0A 1997-09-30 1997-09-30 Dual port buffer Ceased GB9720811D0 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
GBGB9720811.0A GB9720811D0 (en) 1997-09-30 1997-09-30 Dual port buffer
EP98307887A EP0905610B1 (en) 1997-09-30 1998-09-29 Dual port buffer
DE69819648T DE69819648T2 (de) 1997-09-30 1998-09-29 Zweitorpuffer
US09/164,227 US6249875B1 (en) 1997-09-30 1998-09-30 Interface circuit using plurality of synchronizers for synchronizing respective control signals over a multi-clock environment
JP10278224A JPH11175313A (ja) 1997-09-30 1998-09-30 デュアルポートバッファ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GBGB9720811.0A GB9720811D0 (en) 1997-09-30 1997-09-30 Dual port buffer

Publications (1)

Publication Number Publication Date
GB9720811D0 true GB9720811D0 (en) 1997-12-03

Family

ID=10819871

Family Applications (1)

Application Number Title Priority Date Filing Date
GBGB9720811.0A Ceased GB9720811D0 (en) 1997-09-30 1997-09-30 Dual port buffer

Country Status (5)

Country Link
US (1) US6249875B1 (https=)
EP (1) EP0905610B1 (https=)
JP (1) JPH11175313A (https=)
DE (1) DE69819648T2 (https=)
GB (1) GB9720811D0 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6700872B1 (en) * 1998-12-11 2004-03-02 Cisco Technology, Inc. Method and system for testing a utopia network element
KR100443014B1 (ko) * 2001-12-24 2004-08-04 엘지전자 주식회사 듀얼포트램을 이용한 상이위상 클럭간 데이터 전송 장치
US7100065B2 (en) * 2003-05-09 2006-08-29 Hewlett-Packard Development Company, L.P. Controller arrangement for synchronizer data transfer between a core clock domain and bus clock domain each having its own individual synchronizing controller
US7194650B2 (en) * 2003-05-09 2007-03-20 Hewlett-Packard Development Company, L.P. System and method for synchronizing multiple synchronizer controllers
US6864722B2 (en) * 2003-05-09 2005-03-08 Hewlett-Packard Development Company, L.P. Phase detector for a programmable clock synchronizer
US7219251B2 (en) * 2003-05-09 2007-05-15 Hewlett-Packard Development Company, L.P. Programmable clock synchronizer
US7480357B2 (en) * 2003-05-10 2009-01-20 Hewlett-Packard Development Company, L.P. System and method for effectuating the transfer of data blocks across a clock boundary
US7623482B2 (en) * 2003-05-10 2009-11-24 Hewlett-Packard Development Company, L.P. System and method for effectuating the transfer of data blocks including a header block across a clock boundary
US7340631B2 (en) * 2004-07-23 2008-03-04 Hewlett-Packard Development Company, L.P. Drift-tolerant sync pulse circuit in a sync pulse generator
US7382847B2 (en) * 2004-07-23 2008-06-03 Hewlett-Packard Development Company, L.P. Programmable sync pulse generator
US7119582B2 (en) * 2004-07-23 2006-10-10 Hewlett-Packard Development Company, Lp. Phase detection in a sync pulse generator
US20060023819A1 (en) * 2004-07-29 2006-02-02 Adkisson Richard W Clock synchronizer
US7436917B2 (en) * 2004-07-29 2008-10-14 Hewlett-Packard Development Company, L.P. Controller for clock synchronizer
US9138825B2 (en) * 2005-10-07 2015-09-22 Illinois Tool Works Inc. Wireless communication system for welding-type devices
JP4851964B2 (ja) * 2007-03-05 2012-01-11 Ｎｅｃアクセステクニカ株式会社 デュアルポートメモリを用いた同期化回路
EP2320327A1 (en) * 2009-11-09 2011-05-11 Imec A data transferring device
EP2360598A1 (en) * 2010-02-12 2011-08-24 Blue Wonder Communications GmbH Method and device for synchronizing data broadcasts
US8826062B2 (en) 2011-05-23 2014-09-02 Intel Mobile Communications GmbH Apparatus for synchronizing a data handover between a first clock domain and a second clock domain through phase synchronization
US8918666B2 (en) * 2011-05-23 2014-12-23 Intel Mobile Communications GmbH Apparatus for synchronizing a data handover between a first and second clock domain through FIFO buffering
US9706508B2 (en) * 2013-04-05 2017-07-11 Honeywell International Inc. Integrated avionics systems and methods
US10902171B1 (en) * 2019-07-09 2021-01-26 SiFive, Inc. Clock crossing interface for integrated circuit generation
US11321511B2 (en) 2019-07-09 2022-05-03 SiFive, Inc. Reset crossing and clock crossing interface for integrated circuit generation

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5782217A (en) * 1980-11-10 1982-05-22 Matsushita Electric Ind Co Ltd Pcm recorder possible for synchronizing run
US4769792A (en) 1986-10-28 1988-09-06 Kabushiki Kaisha Toshiba Semiconductor memory device with voltage bootstrap
US5146477A (en) * 1987-03-17 1992-09-08 Antonio Cantoni Jitter control in digital communication links
US4805171A (en) * 1987-07-10 1989-02-14 Solid State Systems, Inc. Unitary PCM rate converter and multiframe buffer
US5029124A (en) * 1988-05-17 1991-07-02 Digital Equipment Corporation Method and apparatus for providing high speed parallel transfer of bursts of data
JP2536929B2 (ja) * 1989-07-21 1996-09-25 富士通株式会社 位相整合回路
DE4011241B4 (de) * 1990-04-06 2005-06-02 Micronas Gmbh Digitale Fernsehsignalverarbeitungsschaltung mit orthogonalem Ausgangstakt
US5933580A (en) * 1991-09-04 1999-08-03 Canon Kabushiki Kaisha Scanner printer server
US5379384A (en) * 1992-06-05 1995-01-03 Intel Corporation Configuration data loopback in a bus bridge circuit
US5509038A (en) * 1994-04-06 1996-04-16 Hal Computer Systems, Inc. Multi-path data synchronizer system and method
US5469851A (en) * 1994-08-09 1995-11-28 Hewlett-Packard Company Time multiplexed digital ultrasound beamformer
JPH0876713A (ja) * 1994-09-02 1996-03-22 Komatsu Ltd ディスプレイ制御装置
KR0177731B1 (ko) * 1994-09-15 1999-05-15 정장호 망동기용 디지탈 위상동기루프 제어방법
US5537362A (en) 1994-12-06 1996-07-16 National Semiconductor Corporation Low-voltage EEPROM using charge-pumped word lines
US5822341A (en) * 1995-04-06 1998-10-13 Advanced Hardware Architectures, Inc. Multiport RAM for use within a viterbi decoder
SG77135A1 (en) * 1996-04-26 2000-12-19 Texas Instruments Inc Method and system for assigning a channel number to a received data packet
US6088272A (en) * 1997-10-24 2000-07-11 Oki Data Corporation Data output system

Also Published As

Publication number Publication date
JPH11175313A (ja) 1999-07-02
EP0905610A1 (en) 1999-03-31
US6249875B1 (en) 2001-06-19
EP0905610B1 (en) 2003-11-12
DE69819648D1 (de) 2003-12-18
DE69819648T2 (de) 2004-09-30

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Legal Events

Date Code Title Description
AT Applications terminated before publication under section 16(1)