GB9704722D0 - Polysilicon CMP process for high-density DRAM cell structures - Google Patents

Polysilicon CMP process for high-density DRAM cell structures

Info

Publication number
GB9704722D0
GB9704722D0 GBGB9704722.9A GB9704722A GB9704722D0 GB 9704722 D0 GB9704722 D0 GB 9704722D0 GB 9704722 A GB9704722 A GB 9704722A GB 9704722 D0 GB9704722 D0 GB 9704722D0
Authority
GB
United Kingdom
Prior art keywords
cmp process
cell structures
dram cell
density dram
polysilicon cmp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB9704722.9A
Other versions
GB2322964B (en
GB2322964A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to GB9704722A priority Critical patent/GB2322964B/en
Priority to JP9060243A priority patent/JPH10256502A/en
Priority to DE19710961A priority patent/DE19710961C2/en
Priority to FR9703423A priority patent/FR2761198B1/en
Publication of GB9704722D0 publication Critical patent/GB9704722D0/en
Publication of GB2322964A publication Critical patent/GB2322964A/en
Application granted granted Critical
Publication of GB2322964B publication Critical patent/GB2322964B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
GB9704722A 1997-03-07 1997-03-07 Polysilicon CMP process for high-density DRAM cell structures Expired - Fee Related GB2322964B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB9704722A GB2322964B (en) 1997-03-07 1997-03-07 Polysilicon CMP process for high-density DRAM cell structures
JP9060243A JPH10256502A (en) 1997-03-07 1997-03-14 Polysilicon cmp process for high-density dram cell
DE19710961A DE19710961C2 (en) 1997-03-07 1997-03-17 Method of manufacturing a semiconductor device with a capacitor
FR9703423A FR2761198B1 (en) 1997-03-07 1997-03-20 POLYSILICON CMP PROCESS FOR HIGH DENSITY DRAM CELL STRUCTURES

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB9704722A GB2322964B (en) 1997-03-07 1997-03-07 Polysilicon CMP process for high-density DRAM cell structures
JP9060243A JPH10256502A (en) 1997-03-07 1997-03-14 Polysilicon cmp process for high-density dram cell
DE19710961A DE19710961C2 (en) 1997-03-07 1997-03-17 Method of manufacturing a semiconductor device with a capacitor
FR9703423A FR2761198B1 (en) 1997-03-07 1997-03-20 POLYSILICON CMP PROCESS FOR HIGH DENSITY DRAM CELL STRUCTURES

Publications (3)

Publication Number Publication Date
GB9704722D0 true GB9704722D0 (en) 1997-04-23
GB2322964A GB2322964A (en) 1998-09-09
GB2322964B GB2322964B (en) 2001-10-17

Family

ID=27438574

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9704722A Expired - Fee Related GB2322964B (en) 1997-03-07 1997-03-07 Polysilicon CMP process for high-density DRAM cell structures

Country Status (4)

Country Link
JP (1) JPH10256502A (en)
DE (1) DE19710961C2 (en)
FR (1) FR2761198B1 (en)
GB (1) GB2322964B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100270210B1 (en) * 1998-04-25 2000-10-16 윤종용 DRAM cell capacitor and method of manufacturing the same
KR100301370B1 (en) * 1998-04-29 2001-10-27 윤종용 Method for manufacturing dram cell capacitor
FR2835970B1 (en) * 2002-02-11 2005-02-25 Memscap ELECTRONIC COMPONENT INCLUDING A CAPACITIVE STRUCTURE

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164337A (en) * 1989-11-01 1992-11-17 Matsushita Electric Industrial Co., Ltd. Method of fabricating a semiconductor device having a capacitor in a stacked memory cell
DD299990A5 (en) * 1990-02-23 1992-05-14 Dresden Forschzentr Mikroelek One-transistor memory cell arrangement and method for its production
US5084405A (en) * 1991-06-07 1992-01-28 Micron Technology, Inc. Process to fabricate a double ring stacked cell structure
US5150276A (en) * 1992-01-24 1992-09-22 Micron Technology, Inc. Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings
KR960003498B1 (en) * 1992-06-18 1996-03-14 금성일렉트론주식회사 Process of manufacturing capacitor for semiconductor device
DE4221431A1 (en) * 1992-06-30 1994-01-05 Siemens Ag Manufacturing process for a key capacitor
DE4223878C2 (en) * 1992-06-30 1995-06-08 Siemens Ag Manufacturing method for a semiconductor memory device
US5292677A (en) * 1992-09-18 1994-03-08 Micron Technology, Inc. Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts
KR960005246B1 (en) * 1992-10-21 1996-04-23 현대전자산업주식회사 Storage electrode manufacture of capacitor
KR100388519B1 (en) * 1995-02-22 2003-09-19 마이크론 테크놀로지, 인크. Method for forming a bit line on a capacitor array of a memory cell and an integrated circuit and a semiconductor memory device using the same
US5539230A (en) * 1995-03-16 1996-07-23 International Business Machines Corporation Chimney capacitor
JP2682509B2 (en) * 1995-04-28 1997-11-26 日本電気株式会社 Method for manufacturing semiconductor device
US5604146A (en) * 1996-06-10 1997-02-18 Vanguard International Semiconductor Corporation Method to fabricate a semiconductor memory device having an E-shaped storage node

Also Published As

Publication number Publication date
DE19710961C2 (en) 2002-02-28
JPH10256502A (en) 1998-09-25
DE19710961A1 (en) 1998-09-24
GB2322964B (en) 2001-10-17
FR2761198A1 (en) 1998-09-25
GB2322964A (en) 1998-09-09
FR2761198B1 (en) 1999-04-30

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20030307