GB907552A - Improvements relating to electrical delay line circuits - Google Patents

Abstract

907,552. Pulse delaying circuits. ELECTRIC & MUSICAL INDUSTRIES Ltd. Jan. 1, 1959 [Jan. 9, 1958], No. 845/58. Class 40 (6). In a pulse delaying circuit in which a source of pulses is applied via a delay line to a variable load impedance which may vary within a range including an impedance greater than the characteristic impedance of the delay line a biased rectifier is connected across the load so that when the load impedance exceeds that of the line the rectifier conducts to reduce reflections set up in the line of the same polarity as the input pulses. The Figure shows a pulse delaying circuit in which pulses of amplitude V from a source 1 are applied via delay line to a variable load impedance Z the impedance of which may vary within a range which includes values greater than the characteristic impedance of the delay line and may be, for example, the input circuit of a transistor. Rectifier 4 is biased to V volts by a source 5 so that when the impedance of the load 3 exceeds that of the delay line and pulses are produced across it of amplitude greater than V the rectifier 4 conducts and the pulses across the load 3 are limited to the amplitude V of the input pulses. In this way reflections at the termination of the line due to the leading edge of an input pulse are reduced to a minimum. A further rectifier 6 conducts when the potential drop between the output terminals of the delay line due to the trailing edge of the pulse exceeds the amplitude V so that reflections due to the trailing edge arriving at the unmatched load impedance 3 are also reduced to a minimum.